Broadcom BCM5722 Programmer's Manual page 195

Programmer's Guide BCM5722
10/15/07
BIOS
The BIOS detects if a PCI device supports Expansion ROM or not by writing the value 0xFFFFFFFE to
Expansion_ROM_Base_Register (register 0x30 of PCI configuration). The BIOS then reads back from this register. If the
value is nonzero, then this PCI device supports Expansion ROM; otherwise, it does not. The BCM5722 Ethernet controller
returns a non-zero value appropriate for the expansion ROM size selected in NVRAM (see "Common Data Structures" on
page 42) when Expansion ROM is enabled (PCI_State.PCI_Expansion_ROM_Desired bit is set to 1). On the other hand, if
the PCI_Expansion_ROM_Desired bit cleared, then the BCM5722 Ethernet controller returns a value of 0x00000000. This
indicates to the BIOS that no Expansion ROM is supported.
If a PCI device supports Expansion ROM, the BIOS will assign a Expansion Base address to the device. It then checks for
a valid ROM header (0x55 0xAA as first two bytes, and so forth) and checksum. If the ROM header and image are valid, the
BIOS will copy the Expansion ROM image to HOST's Upper Memory Block (UMB) and invoke the initializing entry point.
Preboot Execution Environment
Preboot Execution Environment (PXE) is implemented as an Expansion ROM in the NIC implementation. In the LOM
implementation, PXE normally resides in the system BIOS. In the NIC implementation, PXE image is stored in the NVRAM.
Upon power on reset of the BCM5722 Ethernet controller, the RX RISC will load the bootcode from the NVRAM into RX
RISC scratch pad and execute. This bootcode will program the device with programmable manufacturing information (such
as MAC address, PCI vendor ID/device ID, etc.). If PXE is enabled, the bootcode responds to the Expansion ROM accesses
of system BIOS.
Bootcode is executed whenever the BCM5722 Ethernet controller is reset via PCI Reset or S/W device reset. PXE
initialization should only be necessary after a PCI reset. The bootcode differentiates PCI Reset and driver initiated software
reset by checking content in Internal Memory at 0xb50. If the content is 0x4B657654, then the reset is due to driver initiated
software reset. Therefore, the device driver has to initialize 0xb50 with 0x4B657654 before issuing a S/W device reset.
P M
OWER ANAGEMENT
D
ESCRIPTION
The BCM5722 Ethernet controller is compliant with the PCI v1.1 power management specification. The MAC is
programmable to two ACPI states: D0 and D3. The D0 state is a full power, operational mode—all the MAC core functions
run at the highest clocking frequency, and components are fully functional. The MAC may be either initialized or un-initialized
in the D0 ACPI state. An un-initialized D0 state is entered through a device reset or PME event; the MAC functional blocks
are not started and initialized. Host software must reset/initialize hardware blocks to transition the device to a D0 initialized
(active) state. The D0 active state places the device into a full power/operational mode. Receive and transmit data paths are
fully operational, and the PCI block is initialized for bus mastering DMA.
Host device drivers do not differentiate between D3 hot and D3 cold states. ACPI-compliant device drivers are unloaded and
quiescent in the D3 state and PCI slot power state is transparent. When the MAC is in D3 hot state, PCI slot power (3.3V or
5.0V) is available to power the PCI I/O pins. The PCI configuration and memory space may be accessed in D3 hot state.
The core clock must remain enabled, so the MAC can respond to PCI configuration and memory transactions. The
Disable_Core_Clock bit, in the PCI Clock Control register (see "PCI Clock Control Register (Offset 0x74)" on page 207)
enables/disables clocking in the core clock domain. A D3 cold state provides only the PCI Vaux supply—PCI slot power is
not present. The MAC will consume a maximum of 375 mA in a D3 cold power management mode.
Bro adco m Co rp or atio n
Document 5722-PG101-R Power Management Page 136