Programmer's Guide
10/15/07
100BASE-X False Carrier Sense Counter
Table 549: 100BASE-X False Carrier Sense Counter (Address 19d, 13h)
Bit
Name
15:8
SMII Overrun/Underrun
Counter [7:0]
7:0
False Carrier Sense
Counter [7:0]
Overrun/Underrun Counter [7:0]
The overrun/underrun counter increments each time the PHY detects an overrun or underrun of the receive FIFOs. The
counter automatically clears itself when read. When the counter reaches its maximum value, FFh, it stops counting overrun/
underrun errors until cleared.
False Carrier Sense Counter [7:0]
This counter increments each time the PHY detects a false carrier on the receive input. This counter automatically clears
itself when read. When the counter reaches its maximum value, FFh, it stops counting false carrier sense errors until cleared.
100BASE-X Disconnect Counter
Bit
Name
15
SMII Fast RXD
14
SMII Slow RXD
13:8
Reserved
7:0
Reserved
R/W = Read/Write, RO = Read only, SC = Self Clear, LL = Latched Low, LH = Latched High, LL and LH Clear after read
operation. Use default values of reserved bit(s) when writing to reserved bit(s).
SMII Fast RXD
Extended FIFO operation only. Bit 15 of the Disconnect Counter register indicates the FIFO state machine has detected fast
receive data relative to the reference input.
SMII Slow RXD
Extended FIFO operation only. Bit 14 of the Disconnect Counter register indicates the FIFO state machine has detected slow
receive data relative to the reference input.
Document
5722-PG101-R
R/W
Description
R/W
Number of overruns/underruns since last read
R/W
Number of false carrier sense events since last read
Table 550: 100BASE-X Disconnect Counter (Address 20d, 14h)
R/W
Description
R/O
1 = In extended FIFO mode, detect fast receive data
0 = Normal
R/O
0 = Normal
1 = In extended FIFO mode, detect slow receive data
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Bro adco m Co rp or atio n
Transceiver Registers (BCM5906/BCM5906M)
BCM5722
Default
00h
00h
Default
0
0
000010
00h
Page 496
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