Table 111: Power Management Capability Register (Offset 0X48); Table 112: Pm Next Capabilities Pointer Register (Offset 0X49); Table 113: Power Management Capabilities Register (Offset 0X4A) - Broadcom BCM5722 Programmer's Manual

BCM5722
PCI P M
OWER ANAGEMENT
Devices that support PCI Power Management must support a block of registers that is part of the Capabilities List in PCI
Configuration Space. The PCI Power Management Register Block is located at offset 0x48. The device supports the
following PCI Power Management registers.
P M
OWER ANAGEMENT
This 8-bit register identifies this item in the Capabilities List as a PCI Power Management register set.
Bit Field
7:0 PM Capability ID
PM N C
EXT APABILITIES
This register points to the next item in the Capabilities List.
Bit Field
7:0 PM Next Capabilities
P M
OWER ANAGEMENT

Table 113: Power Management Capabilities Register (Offset 0x4A)

Bit Field
15:11 PME Support
10 D2 Support
9 D1 Support
Page 197 PCI Power Management Capabilities
C
APABILITIES
C ID R
APABILITY

Table 111: Power Management Capability Register (Offset 0x48)

Description
Identifies this item as Power Management capabilities.
P R
OINTER EGISTER

Table 112: PM Next Capabilities Pointer Register (Offset 0x49)

Description
Points to the next capabilities block which is for Vital
Product Data (VPD).
C R
APABILITIES EGISTER
Description
Indicates the power states in which the device may assert
PME. A 0 for any bit indicates that the device is not capable
of asserting the PME pin signal while in that power state.
• Bit 11 = PME can be asserted from D0. Default is 0.
• Bit 12 = PME can be asserted from D1. Default is 0.
• Bit 13 = PME can be asserted from D2. Default is 0.
• Bit 14 = PME can be asserted from D3Hot. Default is 1.
• Bit 15 = PME can be asserted from D3Cold. Default
depends on the presence of an Aux power supply.
Auxiliary power is detected by the presence of power on
the VAUX_PRSNT signal pin.
Indicates whether the device supports the D2 power
management state. This device does not support D2, so this
bit is hardwired to 0.
Indicates whether the device supports the D1 power
management state. This device does not support D1, so this
bit is hardwired to 0.
Bro adco m C orp or atio n
(O 0
EGISTER FFSET X
(O 0 49)
FFSET X
(O 0 4A)
FFSET X
Programmer's Guide
48)
Init
01h
Init
50h
Init
01000 if Aux
is not
present
11000 if Aux
present
0
0
Document 5722-PG101-R
10/15/07
Access
RO
Access
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Access
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