Programmer's Guide
10/15/07
NVM C
R
OMMAND
EGISTER
Bit
Field
Description
31:28
Policy Error
Reports Address Lockout Policy Error violations.
27:18
Reserved
–
17
seeprom
Write 1 to this bit to start external EEPROM reset sequence. HW checks the START
reset start
condition and issues 9 dummy cycles to reset the external EEPROM.
(BCM5906
only.
Reserved (all
–
others)
16
seeprom
A value of "1" signals that external eeprom reset sequence is done.
reset done
(BCM5906
only.
Reserved (all
–
others)
15:9
Reserved
–
8
last
When this bit is set, the next command sequence is interpreted as the last one of a
burst and any cleanup work is done. This means that the buffer is written to flash
memory if needed on a write.
7
first
This bit is passed to the SEE_FSM or SPI_FSM if the pass_mode bit is set.
6
erase
The erase command bit. Set high to execute an erase. This bit is ignored if the wr
is clear.
5
wr
The Write/Not_Read command bit. Set to execute write or erase.
4
doit
Command from software to start the defined command. The done bit must be clear
before setting this bit. This bit is self clearing and will remain set while the command
is active.
3
done
Sequence completion bit that is asserted when the command requested by
assertion of the doit bit has completed. The done bit will be cleared while the
command is in progress. The done bit will stay asserted until doit is reasserted or
the done bit is cleared by writing a 1 to the done bit. The done bit is the FLSH_ATTN
signal.
2:1
Reserved
–
0
Reset
When set, the entire NVM state machine is reset. This bit is self clearing.
NVM S
R
TATUS
EGISTER
Bit
Field
31:13
Reserved
7:4
SEE_FSM State
7:4
SEE_FSM State
3:0
SPI_FSM State
Document
5722-PG101-R
(O
0
7000)
FFSET
X
Table 395: NVM Command Register (Offset 0x7000)
(0
7004H)
X
Table 396: NVM Status Register (0x7004H)
Description
–
State Machine Values (TBD)
State Machine Values (TBD)
State Machine Values (TBD)
Bro adco m Co rp or atio n
Init
0
0
0
Non-Volatile Memory Interface Registers
BCM5722
Init
Access
0
RO
0
RO
0
R/W
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
WTC
0
RO
0
R/W
Access
RO
RO
RO
Page 370
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