Table 538: Control Register (Address 00D, 00H) - Broadcom BCM5722 Programmer's Manual

Programmer's Guide
10/15/07
MII R D
EGISTER ETAILED
The following tables describe individual register bits and their function.
MII Control Register
Bit Name
15 Soft Reset
14 Loopback
13 Forced Speed Selection
12 Auto-Negotiation Enable
11 Power Down
10 Isolate
9 Restart Auto-Negotiation
8 Duplex Mode
7:0 Reserved
Soft Reset
To reset the PHY core by software control, a 1 must be written to bit 15 of the Control Register using an MII write operation.
The bit clears itself after the reset process is complete, and need not be cleared using a second MII write. Writes to other
Control Register bits will have no effect until the reset process is completed, which requires approximately 1 µs. Writing a 0
to this bit has no effect. Since this bit is self-clearing, after a few cycles from a write operation, it returns a 1 when read.
Loopback
The PHY core is placed into loopback mode by writing a 1 to bit 14 of the Control Register. The loopback mode is cleared
by writing a 0 to bit 14 of the control register, or by resetting the chip. When this bit is read, it returns a 0 when the chip is in
software- controlled loopback mode, otherwise it returns a 0.
Forced Speed Selection
If auto-negotiation is enabled, this bit has no effect on the speed selection. However, if auto-negotiation is disabled by
software control, the operating speed of the PHY core can be forced by writing the appropriate value to bit 13 of the Control
Register. Writing a 1 to this bit forces 100BASE-X operation, while writing a 0 forces 10BASE-T operation. When this bit is
read, it returns the value of the software-controlled forced speed selection only. To read the overall state of forced speed
selection, from hardware or software control, use bit 2 of the Auxiliary Error and General Status Register, 1Ch.
Document 5722-PG101-R
D
ESCRIPTION

Table 538: Control Register (Address 00d, 00h)

R/W
R/W
(SC)
R/W
R/W
R/W
RO
R/W
R/W
(SC)
R/W
–
Bro adco m Co rp or atio n
Description
1 = PHY reset
0 = Normal operation
1 = Loopback mode
0 = Normal operation
1 = 100 Mbps
0 = 10 Mbps
1 = Auto-negotiation enable
0 = Auto-negotiation disable
0 = Normal operation
1 = Electrically isolate PHY from SMII
0 = Normal operation
1 = Restart auto-negotiation process
0 = Normal operation
1 = Full-Duplex
0 = Half-duplex
–
Transceiver Registers (BCM5906/BCM5906M)
BCM5722
Default
0
0
1
1
0
0
0
0
0
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