Broadcom BCM5722 Programmer's Manual page 445

Programmer's Guide
10/15/07
Bit Field
19 Ignore_hotplug_msg
18–16 Msi_multmsg_capable
15:12 Data_select_limit
11 Enable_pcie_1_1_pl
10 Enable_pcie_1_1_dl
9 Enable_pcie_1_1_tl
8–7 Reserved
6 Pcie_power_budget_cap_enable
Document 5722-PG101-R
Table 414: Transaction Configuration Register (0x7C04) (Cont.)
Description
Allow the device to ignore Hot-Plug Messages
• 0 = Decode Hot-Plug Message
• 1 = Ignore Hot-Plug Message
MSI Multiple Message Capable. This field is
copied over to the MSI Control Field in the
Config.vhd. System software read the
Multiple Message Capable field to determine
the number of requested messages.
• 000 = 1
• 001 = 2
• 010 = 4
• 011 = 8
• 100 = 16
The BCM5722, BCM5755, BCM5755M,
BCM5756M, BCM5757, BCM5754,
BCM5754M, BCM5787, and BCM5787M
devices can only request a maximum of 1 MSI
Message.
This parameter is used in the PCIe Power
Budget Capability Structure to determine the
number of Power Conditions that the device
support. Default is 4 which means that the
device supports four different types of Power
Conditions. The BCM5722, BCM5755,
BCM5755M, BCM5756M, BCM5757,
BCM5754, BCM5754M, BCM5787, and
BCM5787M devices can support up to 8
different power conditions.
This bit enables PCIe 1.1 compliance
changes in the Physical Layer.
• 1 = Enable Compliance
• 0 = Disable Compliance
This bit enables PCIe1.1 compliance changes
in the Data Link Layer. This bit is not used.
• 1 = Enable Compliance
• 0 = Disable Compliance
This bit enables PCIe1.1 compliance changes
in the Transaction Layer specifically for
masking training error from the physical layer
• 1 = Mask Training Error
• 0 = Allow Training Error to log
Spares
This bit is used to control the present of the
PCIe Power Budget Capability Structure.
• 1 = Enable
• 0 = Disable
Bro adco m Co rp or atio n
BCM5722
Access Reset Init
RW Core 1
RW Core 0x0
RW Core 0x0
RW Core 1
RW Core 1
RW Core 1
RW Core 0x1
RW Core 0
PCIe Registers Page 386