Broadcom BCM5722 Programmer's Manual page 557

Programmer's Guide
10/15/07
HSQ:LSQ
Extends or decreases the squelch levels for detection of incoming 10BASE-T data packets. The default squelch levels
implemented are those defined in the IEEE standard. The high-squelch and low-squelch levels are useful for situations
where the IEEE- prescribed levels are inadequate. The squelch levels are used by the CRS/link block to filter out noise and
recognize only valid packet preambles and link integrity pulses. Extending the squelch levels allows the PHY core to operate
properly over longer cable lengths. Decreasing the squelch levels may be useful in situations where there is a high level of
noise present on the cables. Reading these two bits returns the value of the squelch levels.
Edge Rate [1:0]
Control bits used to program the transmit DAC output edge rate in 100BASE-TX mode. These bits are logically ANDed with
the ER[1:0] input pins to produce the internal edge-rate controls (Edge_Rate[1] AND ER[1], Edge_Rate[0] AND ER[0]).
Auto-Negotiation Indicator
A read-only bit that indicates whether auto-negotiation has been enabled or disabled on the PHY core. A combination of a
1 in bit 12 of the Control register and a logic 1 on the ANEN input pin is required to enable auto-negotiation. When auto-
negotiation is disabled, bit 3 of the Auxiliary Control register returns a 0. At all other times, it returns a 1.
Force100/10 Indication
A read-only bit that returns a value of 0 when one of following two cases is true:
• The ANEN pin is low AND the F100 pin is low
• Bit 12 of the Control register has been written as 0 AND bit 13 of the Control register has been written as 0. When bit 8
of the Auxiliary Control register is 0, the speed of the chip is 10BASE-T.
In all other cases, either the speed is not forced (auto-negotiation is enabled), or the speed is forced to 100BASE-X.
Speed Indication
Bit 1 of the Auxiliary Control register is a read-only bit that shows the true current operation speed of the PHY core. A 1 bit
indicates 100BASE-X operation, whereas a 0 indicates 10BASE-T operation. Note that while the auto-negotiation exchange
is being performed, the PHY core is always operating at 10BASE-T speed.
Full-Duplex Indication
Bit 0 of the Auxiliary Control register is a read-only bit that returns a 1 when the PHY is in full-duplex mode. In all other modes,
it returns a 0.
Document 5722-PG101-R
Bro adco m Co rp or atio n
Transceiver Registers (BCM5906/BCM5906M)
BCM5722
Page 498