Figure 58: Word Swap Enable Translation On 32-Bit Pci (No Byte Swap); Figure 59: Byte Swap Enable Translation On 32-Bit Pci (No Word Swap); Figure 60: Byte And Word Swap Enable Translation On 32-Bit Pci - Broadcom BCM5722 Programmer's Manual

BCM5722
If Word Swapping is not enabled, and the host made a 32-bit read request to address 0x08, the four bytes of data returned
on the PCI bus would actually be the NIC Ring Address rather than the Max_Len and Flags fields. This initially might seem
counter-intuitive, but is explained in
Endian) referenced on-chip data structures as they are defined in the BCM5722 Ethernet controller data sheet, the driver
should set the Enable Endian Word Swap bit. By setting this bit, the translation would be as follows:
Internal Byte Ordering
31
0x00
88 89
0x04
8C 8D

Figure 58: Word Swap Enable Translation on 32-Bit PCI (No Byte Swap)

The only side effect for a little endian host that sets the Enable Endian Word Swap bit would be that the driver would have
to perform an additional word swap on any 64-bit fields (e.g., a 64-bit physical address) that were given to the driver by the
Network Operating System (NOS).
Little-endian hosts will not want to set the Enable Endian Byte Swap bit for target accesses. This bit is intended to be used
by big endian systems that needed PCI data (little endian) translated back to big endian format.
Note: Some big endian systems automatically do this depending on the architecture of the host's PCI to memory
interface.
The following figures show the translation of data when the Enable Endian Byte Swap bit is set:
Internal Byte Ordering
31 16
0x00 88 89
0x04 8C 8D

Figure 59: Byte Swap Enable Translation on 32-Bit PCI (No Word Swap)

Internal Byte Ordering
31 16
0x00 88 89
0x04 8C 8D

Figure 60: Byte and Word Swap Enable Translation on 32-Bit PCI

Page 145 Endian Control (Byte and Word Swapping)
Figure 57 on page
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Bro adco m C orp or atio n
144. Therefore, if a software driver running on an x86 host (Little
31
88
8C
PCI Byte Ordering
31 16
8F 8E
8B 8A
PCI Byte Ordering
31 16
8B 8A
8F 8E
Programmer's Guide
PCI Byte Ordering
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89 8A 8B
8D 8E 8F
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Document 5722-PG101-R
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