Table 150: Msi Capability Id Register (Offset 0Xe8); Table 151: Msi Next Capabilities Pointer Register (Offset 0Xe9) - Broadcom BCM5722 Programmer's Manual

BCM5722
M S
ESSAGE IGNALED
Devices that support Message Signaled Interrupts (MSI) must support a block of registers that is part of the Capabilities List
in PCI Configuration Space. The MSI Register Block is located at offset 0xE8.
Typical use of MSI and, in particular, multiple MSIs is to allow multiple processors to receive interrupt information
independently of the others. The actual use of these in conjunction with the various send and receive queues and status
information is application dependent. The device supports the following MSI registers:
MSI C ID R
APABILITY
This 8-bit register identifies this item in the Capabilities List as a Message Signaled Interrupt (MSI) register set.
Bit Field
7:0 MSI Capability ID
MSI N C
EXT APABILITIES
This register points to the next item in the Capabilities List.
Bit Field
7:0 MSI Next Capabilities
Page 221 Message Signaled Interrupts Capabilities
I
NTERRUPTS
(O 0
EGISTER FFSET

Table 150: MSI Capability ID Register (Offset 0xE8)

Description
Identifies this item as Message Signaled Interrupt
capabilities.
P R
OINTER EGISTER

Table 151: MSI Next Capabilities Pointer Register (Offset 0xE9)

Description
Points to the next capabilities block that is PCIe.
Bro adco m C orp or atio n
C
APABILITIES
E8)
X
(O 0 E9)
FFSET X
Programmer's Guide
10/15/07
Init Access
05h RO
Init Access
0xD0 RO
Document 5722-PG101-R