Broadcom BCM5722 Programmer's Manual page 56

Host programmer interface specification for the netxtreme and netlink family of highly integrated media access controllers
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BCM5722
Programmer's Guide
10/15/07
Table 469: PHY Receive Error Counter (Offset 0x7E20)................................................................................408
Table 470: PHY Receive Framing Error Counter (Offset 0x7E24)..................................................................408
Table 471: PHY Receive Error Threshold Register (Offset 0x7E28) ..............................................................409
Table 472: PHY Test Control Register (Offset 0x7E2C) .................................................................................409
Table 473: PHY/SerDes Control Override Register (Offset 0x7E30)..............................................................411
Table 474: PHY Timing Parameter Override Register (Offset 0x7E34)..........................................................412
Table 475: PHY Hardware Diagnostic 1 Register (Offset 0x7E38).................................................................412
Table 476: PHY Hardware Diagnostic 2 Register (Offset 0x7E3C) ................................................................413
Table 477: Transceiver Register Map.............................................................................................................414
Table 478: MII Control Register (PHY_Addr = 0x1, Reg_Addr = 00h)............................................................415
Table 479: MII Status Register (PHY_Addr = 0x1, Reg_Addr = 01h) .............................................................416
Table 480: PHY Identifier Registers (PHY_Addr = 0x1, Reg_Address 02h)...................................................418
Table 481: PHY Identifier Registers (PHY_Addr = 0x1, Reg_Address 03h)...................................................418
Table 485: Next Page Transmit Register (PHY_Addr = 0x1, Reg_Addr = 07h) .............................................423
Table 488: 1000BASE-T Status Register (PHY_Addr = 0x1, Reg_Addr = 0Ah).............................................426
Table 492: Receive Error Counter (PHY_Addr = 0x1, Reg_Addr = 12h)........................................................432
Table 493: False Carrier Sense Counter (PHY_Addr = 0x1, Reg_Addr = 13h)..............................................432
Table 497: Expansion Register Select Values ................................................................................................434
Table 498: Expansion Register 00h: Receive/Transmit Packet Counter ........................................................435
Table 499: Expansion Register 01h: Expansion Interrupt Status ...................................................................435
Table 500: Expansion register 03h: SerDes Control.......................................................................................436
Table 501: Expansion Register 04h: Multicolor LED Selector ........................................................................437
Table 502: Expansion Register 05h: Multicolor LED Flash Rate Controls......................................................438
Bro adco m C orp or atio n
Page lvi
Document 5722-PG101-R

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