BCM5722
Note: The EMAC debug register (0x8F0) below is R/O. A read to the debug register returns the internal state
value.
Offset
0x400–0x403
0x404–0x407
0x408–0x40b
0x40c–0x40f
0x410–0x413
0x414–0x417
0x418–0x41b
0x41c–0x41f
0x420–0x423
0x424–0x427
0x428–0x42b
0x42c–0x42f
0x430–0x433
0x434–0x437
0x438–0x43b
0x43c–0x43f
0x440–0x44b
0x44c–0x44f
0x450–0x453
0x454–0x457
0x458–0x45b
0x45c–0x45f
0x460–463
0x464–0x467
0x468–0x46b
0x46c–0x46f
0x470–0x473
0x474–0x477
0x478–0x47b
0x47c–0x47f
0x480–04x4ff
0x500–0x503
0x504–0x507
0x508–0x50f
0x510–0x513
0x514–0x517
Page 243
Ethernet MAC Control Registers
Table 189: Ethernet MAC Control Registers—BCM5906 Only
Registers
Ethernet MAC Mode
Ethernet MAC Status
Ethernet MAC Event Enable
LED Control
MAC Address High 1
MAC Address Low 1
MAC Address High 2
MAC Address Low 2
MAC Address High 3
MAC Address Low 3
MAC Address High 4
MAC Address Low 4
WOL pattern Pointer
WOL Pattern Configuration
Transmit Random Backoff
Receive MTU Size Register
Reserved
MI Communication
MI Status
MI Mode
Auto-poll Status
Transmit Mode
Transmit Status
Transmit Lengths
Receive Mode
Receive Status
MAC Hash Register 0
MAC Hash Register 1
MAC Hash Register 2
MAC Hash Register 3
Reserved
Reserved
Low Watermark Maximum Receive Frames Register
Reserved
EtherType Matching Value Register
Protocol ID Offset Register
Bro adco m C orp or atio n
Programmer's Guide
10/15/07
Init
0x00000004
0x00000000
0x00000000
0x82000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x000005F2
0x00000000
0x10000000
0x00000000
0x000c0000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
X
0
0
Document 5722-PG101-R
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