Broadcom BCM5722 Programmer's Manual page 143

Programmer's Guide
10/15/07
21. Configure the DMA Write Water Mark in the DMA Read/Write Control register (see
(Offset 0x6C)" on page
water mark bits (bits19:21) of DMA Read/Write Control register to 011b (for a water mark of 128 bytes). Otherwise (Max
Payload Size is 256 bytes or more), set the DMA write water mark bits (bits19:21) of DMA Read/Write Control register
to 111b (for a water mark of 256 bytes).
22. Set DMA byte swapping (optional). If the host processor architecture is big-endian, the MAC may byte swap both control
and frame data, when acting as a PCI DMA master. Set the Byte_Swap_Non-Frame_Data, Byte_Swap_Data and
Word_Swap_Data bits in the General Mode Control register (see
23. Configure the host-based send ring. Set the Host_Send_BDs bit in the General Mode Control register (see
Register (Offset 0x6800)" on page
24. Indicate Driver is ready to RX traffic. Set the Host_Stack_Up bit in the General Mode Control register (see
Register (Offset 0x6800)" on page
Note: Host software should be careful not to set the Route_Multicast_Frames_to_RISC core bit unless
custom firmware has been developed for multicast frame handling. If this bit is set inadvertently, transmit
frames (e.g., arp, broadcast) may be routed to the RISC Core and the data path will stall. Host software will
observe BD and Frame buffers continue to DMA, but frames will not go out to the wire. Eventually, the MAC
will run out of internal memory and both RX/TX will stall.
25. Configure TCP/UDP pseudo header checksum offloading. This step is relevant when TCP/UDP checksum calculations
are offloaded to the device. The device driver may optionally disable receive and transmit pseudo header checksum
calculations by the device by setting the Receive_No_PseudoHeader _Checksum and
Send_No_PseudoHeader_Checksum bits in the General Mode Control register (see
0x6800)" on page 333). If the Send_No_PsuedoHeader_Checksum bit is set, the host software should make sure of
seeding the correct pseudo header checksum value in TCP/UDP checksum field. Similarly if the
Receive_No_PsuedoHeader_Checksum bit is set, the device driver should calculate the pseudo header checksum and
add it to the TCP/UDP checksum field of the received packet.
26. Configure the frequency of MAC's free running 32-bit timer at offset 0x680C. The Timer_Prescaler bit field in the General
Control Miscellaneous Configuration register (see
sets the local frequency of this timer. This timer at 0x680C offset increments once every Timer_Prescalar number of core
clock cycles. The core clock of the device runs at 66 MHz and hence the device driver software should configure the
Timer_Prescalar field with 0x41, or 65 decimal for the 0x680C timer to increment by one every 1 uS.
27. Configure MAC local memory pool. The MAC uses device local memory to buffer packets that will be DMAed to/from
host memory. Host software needs to program the pool address differently based on the capabilities of the device. The
Mbuf Pool Base Address and Mbuf pool length registers (see
be configured during initialization.
Note: The values of Mbuf Pool Base Address and Mbuf Pool Length registers after device reset are 0x10000
and 0x8000 respectively. The RISC scratch pad memory needs to be reserved out of the Rx Mbuf memory
and hence the bootcode calculates and sets the Mbuf Pool Base Address and Mbuf Pool Length registers.
So, Broadcom recommends to not to change these Mbuf Pool registers from driver software unless the it is
required to load a special firmware from driver. For any reason, if it is required to modify either of the Mbuf
Pool registers from device driver, then driver software should clear the contents of RxMbuf memory and set
the Reset RxMbuf Pointer bit of the Buffer Manager Mode register (offset 0x4400)
Document 5722-PG101-R
205). If the Max Payload Size of PCIe Device Control register is 128 bytes, set the DMA write
333).
333).
Bro adco m Co rp or atio n
"Mode Control Register (Offset 0x6800)" on page
"Miscellaneous Configuration Register (Offset 0x6804)" on page
"Memory Maps and Pool Configuration" on page
BCM5722
"DMA Read/Write Control Register
"Mode Control
"Mode Control
"Mode Control Register (Offset
101) must
Initialization
333).
335)
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