Programmer's Guide
10/15/07
D
C
EVICE
APABILITIES
This register defines operational characteristics that are globally applicable to this device.
Bit
Field
31:28
Reserved
27:26
Captured Slot Power
Limit Scale
25:18
Captured Slot Power
Limit Value
17:15
Reserved
14
Power Indicator
Present
13
Attention Indicator
Present
12
Attention Button
Present
11:9
Endpoint L1
Acceptable Latency
8:6
Endpoint L0s
Acceptable Latency
5
Extended Tag Field
Supported
4:3
Phantom Functions
Supported
Document
5722-PG101-R
R
(O
EGISTER
FFSET
Table 144: Device Capabilities Register (Offset 0xD4)
Description
–
This value specifies the scale used for the Power Limit.
• 00 = 1.0x
• 01 = 0.1x
• 10 = 0.01x
• 11 = 0.001x
This value specifies the upper limit on the power supplied for this device.
–
When set to 1, this value indicates that a Power Indicator is implemented on
this device.
When set to 1, this value indicates that an Attention Indicator is implemented
for this device.
When set to 1, this value indicates that an Attention Button is implemented
for this device.
This value returns the latency that this device can accept when transitioning
from the L1 to the L0 state.
• 000 = Less than 1 µs
• 001 = 1 µs to less than 2 µs
• 010 = 2 µs to less than 4 µs
• 011 = 4 µs to less than 8 µs
• 100 = 8 µs to less than 16 µs
• 101 = 16 µs to less than 32 µs
• 110 = 32 µs to 64 µs
• 111 = Greater than 64 µs
This value returns the total latency that this device can accept when
transitioning from the L0s to L0 state.
• 000 = Less than 64 ns
• 001 = 64 ns to less than 128 ns
• 010 = 128 ns to less than 256 ns
• 011 = 256 ns to less than 512 ns
• 100 = 512 ns to less than 1 µs
• 101 = 1 µs to less than 2 µs
• 110 = 2 µs to 4 µs
• 111 = Greater than 4 µs
This value returns the maximum supported tag field size when this function
acts as a requester.
• 0 = 5-bit tag field
• 1 = 8-bit tag field
This value is hardwired to 0 to indicate that this device only supports a single
function.
Bro adco m Co rp or atio n
0
D4)
X
BCM5722
Init
Access
0
RO
0
RO
0
RO
0
RO
a
0
R/W
0
R/W
0
R/Wa
7h
R/Wa
6h
R/Wa
1
RO
0
RO
PCIe Capabilities
Page 216
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