Table 343: Miscellaneous Configuration Register (Offset 0X6804) - Broadcom BCM5722 Programmer's Manual

BCM5722
M C
ISCELLANEOUS ONFIGURATION
The Miscellaneous Configuration register is used as an extension to the Miscellaneous Local Control register (see
"Miscellaneous Local Control Register (Offset 0x6808)" on page
counters associated with the free-running 32-bit timer inside the device. The prescale function is performed on the clock prior
to advancing the Timer register (see
possible to 1 µs.
Bit Field
31:30 Reserved
29 Disable GRC Reset on PCIe
Block
28 Wire Speed Enable
(BCM5787, BCM5787M,
BCM5754, and BCM5754M
only)
BOND ID 5 (BCM5722,
BCM5755, BCM5755M,
BCM5756M, BCM5757 only)
27 Wire Speed Timer Disable
(BCM5787, BCM5787M,
BCM5754, and BCM5754M
only)
BOND ID 4 (BCM5722,
BCM5755, BCM5755M,
BCM5756M, BCM5757 only)
26 GPHY Power Down Override When this bit is set, the GPHY will be left powered up when
Reserved (BCM5906 only)
25 DDQ_DLL Enable Disable
Reserved (BCM5906 only)
24 RAM Power Down
23 VREG Standby Current Mode When this bit is set, both vreg1 and vreg2 will be put into
22 BIAS IDDQ
Reserved (BCM5906 only)
21 PHY IDDQ
20 Device Power Down
19 Vmain_prsnt (BCM5906 only) Current status of vmain_prsnt signal
Reserved (all others)
18:17 Reserved
Page 335 General Control Registers
R
EGISTER
"Timer Register (Offset 0x680C)" on page

Table 343: Miscellaneous Configuration Register (Offset 0x6804)

Description
–
Setting this bit will prevent PCIe link training during a GRC
reset.
When this bit is set, wire speed detection is enabled.
1 = Super IDDQ Mode Disable
When this bit is set, the wire speed timer is disabled.
–
in the D0 uninitialized state.
• In A1, this bit can only be cleared by a hard reset. A GRC
or PCI reset has no effect.
• In A0, this bit can be cleared by hard-reset, GRC reset,
or PCI reset.
Note: See
–
When this bit is set, the handshake with the GPHY to power
down the DLL is disabled. The IDDQ_DLL_Enable will
always be 1.
–
When this bit is set, all of the RAMs are powered down.
standby current mode (which consumes < 1 mA).
When this bit is set, the BIAS will be powered down.
–
When this bit is set, the PHY will be powered down.
Setting this bit will power down the device (power
consumption is ~20 mW). This bit is cleared by PCI reset.
–
–
Bro adco m C orp or atio n
(O 0 6804)
FFSET X
336). There are several fields used to control several small
"Revision Levels" on page
Programmer's Guide
337) to provide a resolution as close as
Init
0
0
1
ID5
0
ID4
0
8.
0
0
0
0
0
0
0
0
0
0
0
Document 5722-PG101-R
10/15/07
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