Programmer's Guide
10/15/07
PHY T
P
IMING
ARAMETER
Table 474: PHY Timing Parameter Override Register (Offset 0x7E34)
Bit
Field
31
ts1NumOverride
30
txIdleMinOverride
29
txIdle2IdleOverride
28
Reserved
27:16
N_TS1InPollingActive
15:8
txIdleMinTime
7:0
txIdleSettoIdleTime
PHY H
D
ARDWARE
Bit
Field
31:10
Reserved
9:4
Transmit State
Machine State
3:0
Receive State Machine
State
Document
5722-PG101-R
O
R
VERRIDE
EGISTER
Description
Set to override the TS1 number to be sen out in polling active state
with the value in bit (27:16) of this register from the specification
defined value.
Set to override the min time for a transmitter to stay with the value in
bit (15:8) of this register from the specification defined value.
Set to override the Max time for electrical idle transition with the value
in bit (7:0) of this register from the specification defined value.
–
TS1 number needed to be sent in Polling active state.
Minimum time (in symbol time) a transmitter must be in electrical idle. 0x5
Maximum time (in symbol time) to transition to a valid electrical idle
after sending an electrical idle ordered-set.
1 R
IAGNOSTIC
EGISTER
Table 475: PHY Hardware Diagnostic 1 Register (Offset 0x7E38)
Description
–
Transmit state machine states:
• 9:8 = TX Data State
• 7:4 = TX Main State
Receive state machine states 3:0 = RX Main State
Bro adco m Co rp or atio n
(O
0
7E34)
FFSET
X
(O
0
7E38)
FFSET
X
BCM5722
Init
Access
0
R/W
0
R/W
0
R/W
0
RO
0x400
R/W
R/W
0x2
R/W
Init
Access
0
RO
0
RO
0
RO
PCIe Registers
Page 412
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