Figure 61: Wol Functional Block Diagram - Broadcom BCM5722 Programmer's Manual

BCM5722
• PHY auto-negotiation
• BCM5722 Ethernet controller power management
F O
UNCTIONAL VERVIEW
The BCM5722 Ethernet controller is capable of WOL in 10/100 Mbps for copper-based controllers.
Note: When configured for WOL in 1000-Mbps mode, the BCM5722 Ethernet controller draws more than the 375
mA allowed by the PCI specification.
The BCM5722 Ethernet controller uses the TX FIFO to store pattern data (see
transmit engine is disabled and its FIFO is free for use. The TDE fetches data from the memory arbiter starting at a location
specified in the WOL_Pattern_Pointer register. The WOL pattern checker pulls data off the TX FIFO for packet comparisons.
The RX MAC will move incoming frame(s) to the pattern checker, and the remaining RX data path is not utilized. A state
machine controls the Magic Packet comparisons. The WOL state machine will move out of an Idle state, when ACPI power
management is enabled. The WOL state machine will clear the TX FIFO and Match register. The Match register indicates a
positive Magic Packet comparison(s) on a stream.
In 10/100 Mbit mode, data is received once every four clock cycles. The pattern checker compares the first three patterns
in the first cycle, the second three patterns in the second cycle, and the third three patterns in the last cycle. It is idle during
the fourth cycle. In gigabit mode, the pattern checker gets three pattern words from the FIFO at one time.
RX
PCS
RX RX
IO RMII
RX
GMII
Page 159 Wake on LAN Mode/Low-Power
Tx FIFO
Pattern
Checker Managment
Rx MAC

Figure 61: WOL Functional Block Diagram

Bro adco m C orp or atio n
Figure 61). During WOL operation, the
Memory
TDE
Arbiter
Power
Programmer's Guide
10/15/07
Pattern
Data
Internal
Memory
Document 5722-PG101-R