Table 278: Receive Bd Completion Control Registers; Table 279: Receive Bd Completion Mode Register (Offset 0X3000); Table 280: Receive Bd Completion Status Register (Offset 0X3004); Table 281: Nic Standard Receive Bd Producer Index (Offset 0X300C) - Broadcom BCM5722 Programmer's Manual

BCM5722
R BD C
ECEIVE OMPLETION
Offset
0x3000–0x3003
0x3004–0x3007
0x3008–0x300b
0x300c–0x300f
0x3010–0x37ff
R BD C
ECEIVE OMPLETION

Table 279: Receive BD Completion Mode Register (Offset 0x3000)

Bit Field
31:3 Reserved
2 Attn_Enable
1 Enable
0 Reset
R BD C
ECEIVE OMPLETION

Table 280: Receive BD Completion Status Register (Offset 0x3004)

Bit Field
31:3 Reserved
2 Error
1:0 Reserved
NIC S R
TANDARD ECEIVE

Table 281: NIC Standard Receive BD Producer Index (Offset 0x300C)

Bit Field
31:9 Reserved
8–0 NIC Standard Receive BD
Producer Index
Page 291 Receive BD Completion Control Registers
C
ONTROL

Table 278: Receive BD Completion Control Registers

Registers
Receive BD Completion Mode
Receive BD Completion Status
Reserved
NIC Standard Receive BD Producer Index
Reserved
M R
ODE EGISTER
Description
–
When this bit is set to 1, an internal attention is generated
when an error occurs.
This bit controls whether the Receive BD Completion state
machine is active or not. When set to 0, it completes the
current operation and cleanly halts. Until it is completely
halted, it remains one when read.
When this bit is set to 1, the Receive BD Completion state
machine is reset. This is a self-clearing bit.
S R
TATUS EGISTER
Description
–
Receive BD Completion error status.
–
BD P I
RODUCER NDEX
Description
–
–
Bro adco m C orp or atio n
R
EGISTERS
(O 0 3000)
FFSET X
(O 0 3004)
FFSET X
R (O
EGISTER FFSET
Programmer's Guide
10/15/07
Init Access
0 RO
R/W
1 R/W
0 R/W
Init Access
0 RO
RO
0 RO
0 300C)
X
Init Access
0 RO
– R/W
Document 5722-PG101-R