Table 155: Advanced Error Reporting Enhanced Capability Header Register (Offset 0X100); Table 156: Uncorrectable Error Status Register (Offset 0X104) - Broadcom BCM5722 Programmer's Manual

Programmer's Guide
10/15/07
PCI -E
E NHANCED
PCIe devices may optionally support a new configuration space that provides an additional 4 KB of configuration registers
per device. This enhanced configuration space is mapped into host memory through a 256 MB window (enabled through the
Root Complex) that provides access to the 4-KB enhanced configuration space for each of the 64K possible PCIe devices.
Refer to the PCIe specification for additional details on how to access the enhanced configuration space.
The offsets listed for the following registers indicate the offset from the beginning of the enhanced configuration space for
that device.
A E
DVANCED RROR

Table 155: Advanced Error Reporting Enhanced Capability Header Register (Offset 0x100)

Bit Field
31:20 Next Capability Offset Pointer to the Virtual Channel Capability Structure
19:16 Capability Version
15:0 Extended Capability ID This value indicates the type of enhanced capability
U E
NCORRECTABLE
Bit Field
31:21 Reserved
20 Unsupported Request
Error Status
19 ECRC Error Status
18 Malformed TLP Status This bit is set when a Malformed TLP error occurs.
17 Receiver Overflow
Status
16 Unexpected
Completion Status
15 Completer Abort Status This bit is set when a Completer Abort error occurs.
14 Completion Timeout
Status
13 Flow Control Protocol
Error Status
12 Poisoned TLP Status
11:5 Reserved
4 Data Link Protocol
Error Status
3:1 Reserved
0 Training Error Status
Document 5722-PG101-R
C
APABILITIES
R E
EPORTING NHANCED
Description
This value indicates the version of this enhanced capability
header.
header for this block and is hard-wired to one to indicate
the Advanced Error Reporting capability.
S R
RROR TATUS EGISTER

Table 156: Uncorrectable Error Status Register (Offset 0x104)

Description
–
This bit is set when an Unsupported Request Error occurs. 0
This bit is set when an ECRC error occurs.
This bit is set when a Receiver Overflow error occurs.
This bit is set when an Unexpected Completion error
occurs.
This bit is set when a Completion Timeout error occurs.
This bit is set when a Flow Control Protocol error occurs. 0
This bit is set when a Poisoned TLP error occurs.
–
This bit is set when a Data Link Protocol error occurs.
–
This bit is set when a Training error occurs.
Bro adco m Co rp or atio n
C H
APABILITY EADER
(O 0 104)
FFSET X
BCM5722
R (O
EGISTER FFSET
Init Access
0x13C RO
1 RO
1 RO
Init Access
0 RO
W2C
0 W2C
0 W2C
0 W2C
0 W2C
0 W2C
0 W2C
W2C
0 W2C
0 RO
0 W2C
0 RO
0 W2C
PCIe-Enhanced Capabilities
0 100)
X
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