Table 353: Mdi Control Register (Offset 0X6844) - Broadcom BCM5722 Programmer's Manual

Programmer's Guide
10/15/07
Table 352: Serial EEPROM Control Register (Offset 0x6840) (Cont.)
Bit Field
0 Clock Output Tri-state Serial EEPROM clock output tristate control
MDI C R
ONTROL EGISTER
The control register for handling the Management Data Interface, which used to communicate between the physical layer
and management layer.
Bit Field
31:4 Reserved
3 MDI Clock
2 MDI Select
1 MDI Enable
0 MDI Data
S EEPROM D
ERIAL
Note: This register is not applicable to the BCM5906 device.
This 32-bit R/W register specifies the delay between the EEPROM access in 15 ns interval and is used for VPD access.
Since the requirement of back-to-back write for Serial EEPROMs is 10 ms, firmware currently programs this register to
0xA2C2A.
Document 5722-PG101-R
Description
(O 0 6844)
FFSET X

Table 353: MDI Control Register (Offset 0x6844)

Description
–
When enabled, controls the clock signal at the MDC pin. 0
When set, the MDI interface is controlled by this register. 0
When set, the MDI Data Pin is enabled as an output
driver.
When read, returns the value at the MDIO pin. When
written, and the MDI Enable bit is also set, the value is
driven to the MDIO pin.
R (O
ELAY EGISTER FFSET
Bro adco m Co rp or atio n
0 6848)
X
BCM5722
Init Access
0 R/W
Init Access
0 RO
R/W
R/W
0 R/W
0 R/W
General Control Registers Page 342