Read Dma Status Register (Offset 0X4804); Read Dma Programmable Ipv6 Extension Header Register (Offset: 0X4808); Table 310: Read Dma Status Register (Offset 0X4804); Table 311: Read Dma Programmable Ipv6 Extension Header Register (Offset: 0X4808) - Broadcom BCM5722 Programmer's Manual

BCM5722
R DMA S
EAD TATUS
Bit Field
31:11 Reserved
10 Read DMA PCI-X Split Transaction
Timeout Expired
9 Read DMA Local Memory Write
Longer Than DMA Length Error
8 Read DMA PCI FIFO Overread Error Read DMA PCI FIFO Overread Error (PCI read longer
7 Read DMA PCI FIFO Underrun Error Read DMA PCI FIFO Underrun Error.
6 Read DMA PCI FIFO Overrun Error
5 Read DMA PCI Host Address
Overflow Error
4 Read DMA PCI Parity Error
3 Read DMA PCI Master Abort Error
2 Read DMA PCI Target Abort Error
1:0 Reserved
R DMA P
EAD ROGRAMMABLE
Note: This register is not applicable to the BCM5906 device.

Table 311: Read DMA Programmable IPv6 Extension Header Register (Offset: 0x4808)

Bit Field
31 Programmable Extension Header
Type #2 Enable
30 Programmable Extension Header
Type #1 Enable
29:16 Reserved
15:8 Programmable Extension Header
Type #2
7:0 Programmable Extension Header
Type #1
Page 313 Read DMA Control Registers
R (O
EGISTER FFSET

Table 310: Read DMA Status Register (Offset 0x4804)

Description
–
Read DMA PCI-X split transaction timeout expired.
Read DMA Local Memory Write Longer Than DMA Length
Error.
than DMA length).
Read DMA PCI FIFO Overrun Error.
Read DMA PCI Host Address Overflow Error. A host
address overflow occurs when a single DMA read begins
at an address below a multiple of 4 GB and ends at an
address above the same multiple of 4 GB (i.e., the host
memory address transitions from
0xXXXXXXXX_FFFFFFFF to 0xYYYYYYYY_00000000
in a single read). This is a fatal error.
Read DMA PCI Parity Error.
Read DMA PCI Master Abort Error.
Read DMA PCI Target Abort Error.
–
IP 6 E
V XTENSION
Description
This bit enables programmable extension header #2. If
this bit is clear, then the value programmed in bits [15:8] of
this register will be ignored. If this bit is set, then extension
headers will be checked for a type matching the value in
bits [15:8].
This bit enables programmable extension header #1. If
this bit is clear, then the value programmed in bits [7:0] of
this register will be ignored. If this bit is set, then extension
headers will be checked for a type matching the value in
bits [7:0].
Reserved bits
These bits contain the programmable extension header
value for programmable header #2.
These bits contain the programmable extension header
value for programmable header #1.
Bro adco m C orp or atio n
0 4804)
X
H R
EADER EGISTER
Programmer's Guide
10/15/07
Init Access
0 RO
0 W2C
0 W2C
0 W2C
0 W2C
0 W2C
0 W2C
0 W2C
0 W2C
0 W2C
0 W2C
(O : 0 4808)
FFSET X
Init Access
0 R/W
0 R/W
0 RO
0 R/W
0 R/W
Document 5722-PG101-R