Table 404: Nvm Access Register (Offset 0X7024) - Broadcom BCM5722 Programmer's Manual

BCM5722
Bit Field Description
15 REQ3 Software request bit 3. A 1 in this bit indicates that the request5 is active.
14 REQ2 Software request bit 2. A 1 in this bit indicates that the request5 is active.
13 REQ1 Software request bit 1. A 1 in this bit indicates that the request5 is active.
12 REQ0 Software request bit 0. When Req_set0 bit is set, this bit will be set.
11 ARB_WON3 Arbitration won bit 3 (see Bit 8, ARB_WON0).
10 ARB_WON2 Arbitration won bit 2 (see Bit 8, ARB_WON0).
9 ARB_WON1 Arbitration won bit 1 (see Bit 8, ARB_WON0).
8 ARB_WON0 When req0 arbitration is won, this bit will be read as 1. When an operation is
complete, then Req_clr0 must be written to clear this bit. At that point, the next
high priority Arb bit will be set if requested. At any time, only one of the
ARB_WON[5:0] bits will be read as a 1. ARB0 has highest priority, and ARB5 has
lowest priority.
7 REQ_CLR3 Write a 1 to this bit to clear the REQ3 bit.
6 REQ_CLR2 Write a 1 to this bit to clear the REQ2 bit.
5 REQ_CLR1 Write a 1 to this bit to clear the REQ1 bit.
4 REQ_CLR0 Write a 1 to this bit to clear the REQ0 bit.
3 REQ_SET3 Write a 1 to this bit to set the REQ3 bit.
2 REQ_SET2 Write a 1 to this bit to set the REQ2 bit.
1 REQ_SET1 Write a 1 to this bit to set the REQ1 bit.
0 REQ_SET0 Set Software Arbitration request bit 0. This bit is set by writing a 1.
Note: By convention, the bootcode has the highest priority for NVRAM access. It uses software request 0 followed
by host driver software, which uses software request 1. When the host driver software downloads optional firmware
to the BCM5722 Ethernet controller (see
the RX RISC CPU. If the RX RISC CPU is executing bootcode and the ARB_WON0 bit is set when the CPU is
stopped, the host driver software must also set the REQ_CLR0 bit to release the NVRAM lock held by the bootcode,
otherwise, no other software is able to access NVRAM until the BCM5722 Ethernet controller is reset.
NVM A R
CCESS EGISTER
Bit Field
31:2 Reserved
1 NVM Access Write Enable
0 NVM Access Enable
Page 375 Non-Volatile Memory Interface Registers
Table 403: Software Arbitration Register (Offset 0x7020) (Cont.)
"Firmware Download" on page
(O 0 7024)
FFSET X

Table 404: NVM Access Register (Offset 0x7024)

Description
–
When set, allows the NVRAM write command (see the WR bit in
the Table 395 on page
Write Enable bit of the Mode Control register (see
page 333) is 0.
When clear, prevents write access to all other NVM registers,
except for the Software Arbitration Register (see
page 374).
Bro adco m C orp or atio n
92), one of the required steps is to stop
370) to be issued even if the NVRAM
Table 403 on
Programmer's Guide
10/15/07
Init Access
0 RO
0 RO
0 RO
0 RO
0 RO
0 RO
0 RO
0 RO
WO
WO
WO
WO
WO
WO
WO
WO
Init Access
0 RO
0 R/W
Table 342 on
0 R/W
Document 5722-PG101-R