Broadcom BCM5722 Programmer's Manual page 216

BCM5722
To write a value of 0x1000 into 16-bit PHY register at offset 0x0 of a PHY device which is strapped to PHY address 1, perform
the following steps:
1. MI_Communication_Register.Register_Address is set to 0x0.
2. MI_Communication_Register.PHY_Addr is set to 1.
3. MI_Communication_Register.Command is set to 0x1.
4. MI_Communication_Register.Transaction_Data is set to 0x1000
5. MI_Communication_Register.Start_Busy is set to 1.
6. Poll Until MI_Communication_Register.Start_Busy is cleared to 0.
See "Configuring the GMII/MII PHY" on page 153
PHY S
ETUP AND
The device driver can determine link change status in one of the following ways:
• Polling for the link status change by PIO read to the Ethernet MAC status register 0x404 (see
Register (Offset 0x404)" on page
• By reading the Link_State_Changed bit of the status block in the ISR when the device is enabled to generate the link
state change interrupts.
Setup and Initialization Procedure
1. Disable link events. Write the value 0x00 to Ethernet MAC Event Enable register (see
Register (Offset 0x408)" on page
2. Clear link attentions. Write a 1 to Link State Changed bit (bit-12) in the Ethernet MAC Status register (see
Status Register (Offset 0x404)" on page
3. Disable Autopolling mode. Write the value 0xC0000 to the MI Mode register (see
page 252). The Port_Polling bit will be de-asserted.
4. Wait 40 µs for the Auto Poll disable step to complete.
5. Disable the PHY WOL mode. Write 0x02 to the PHY's MDI Auxiliary Control register. This value will enable the Power
Control Shadow register, disable WOL, and configure normal operation.
6. The programmer is strongly encouraged to reference the errata sheet for the physical layer component. Implement the
appropriate workarounds.
7. Acknowledge outstanding interrupts by reading the MDI Interrupt_Status register twice. There are sticky bits, which
require host software to read the register twice, to clear values.
8. Configure the PHY interrupt mask. Clear the Link_Status_Change bit in the MDI Interrupt_Mask register. Each bit in the
MDI Interrupt_Status bit has a 1:1 mapping to bits in the MDI Interrupt_Mask register. Assert all remaining bits to disable/
mask out other interrupt types.
9. Determine link status. Read the MDI Status register (PHY register offset 0x01) twice. There are sticky bits that must be
cleared—second read clears bits latched high.
10. Determine speed and duplex operation. Read the MDI Auxiliary_Status register. The programmer may poll the MDI
Auxiliary_Status register for 20 ms and check the Link_Status pass bit.
11. Store speed/duplex settings in driver state variables. Initialization complete if no link detected.
Page 157 PHY Setup and Initialization
for example code.
I
NITIALIZATION
246).
247). This step de-asserts events for the MI_Interrupt and Link_State_Changed.
246) to clear pending attentions.
Bro adco m C orp or atio n
Programmer's Guide
"Ethernet MAC Status
"Ethernet MAC Event Enable
"Ethernet MAC
"MI Mode Register (Offset 0x454)" on
Document 5722-PG101-R
10/15/07