Table 38: Recommended Bcm5722 Ethernet Controller Host Coalescing Tick Counter Settings; Table 39: Recommended Bcm5722 Ethernet Controller Host Coalescing Frame Counter Settings; Table 40: Recommended Bcm5722 Ethernet Controller Max Coalesced Frames During Interrupt Counter; Settings - Broadcom BCM5722 Programmer's Manual

Programmer's Guide
10/15/07

Table 38: Recommended BCM5722 Ethernet Controller Host Coalescing Tick Counter Settings

Register
Receive Coalescing Ticks
Send Coalescing Ticks
53. Configure the host coalescing BD count. The Receive Max Coalesced BD and Send Max Coalesced BD registers (see
"Receive Max Coalesced BD Count (Offset 0x3C10)" on page 296
on page 296) specify the number of frames processed before an interrupt is driven. Broadcom recommends the settings
shown in Table 39.

Table 39: Recommended BCM5722 Ethernet Controller Host Coalescing Frame Counter Settings

Register
Receive Max Coalesced Frames
Send Max Coalesced Frames
54. Configure the max-coalesced frames during interrupt counter. While host software processes interrupts, this value is
used. See the Receive Max Coalesced Frames During Interrupt and Send Max Coalesced Frames During Interrupt
registers (see "Receive Max Coalesced BD Count (Offset 0x3C10)" on page 296
(Offset 0x3C14)" on page

Table 40: Recommended BCM5722 Ethernet Controller Max Coalesced Frames During Interrupt Counter

Register
Receive Max Coalesced Frames During Interrupt
Send Max Coalesced Frames During Interrupt
55. Initialize host status block address. Host software must write a physical address to the Status Block Host Address
register (see "Status Block Host Address Register (Offset 0x3C38)" on page
must DMA status data. This register accepts a 64-bit value.
56. Enable the host coalescing engine. Set the Enable bit in the Host Coalescing Mode register.
57. Enable the receive BD completion functional block. Set the Enable and Attn_Enable bits in the Receive BD Completion
Mode register (see "Receive BD Completion Mode Register (Offset 0x3000)" on page
58. Enable the receive list placement functional block. Set the Enable bit in the Receive List Placement Mode register (see
"Receive List Placement Mode Register (Offset 0x2000)" on page
59. Enable DMA engines. Set the Enable_FHDE, Enable_RDE, and Enable_TDE bits in the Ethernet Mac Mode register
(see "Ethernet MAC Mode Register (Offset 0x400)" on page
60. Enable and clear statistics. Set the Clear_TX_Statistics, Enable_TX_Statistics, Clear_RX_Statistics, and
Enable_TX_Statistics bits in the Ethernet Mac Mode register (see
page 245).
61. Configure the General Miscellaneous Local Control register (see
on page 336). Set the Interrupt_On_Attention bit in order for MAC to assert an interrupt whenever any of the attention
bits in the CPU event register are asserted. Also set the Auto SEEPROM Access bit for MAC to access the SEEPROM
through the SEEPROM address and data registers.
62. Write a value of zero to the Interrupt Mailbox 0 low word (see
Document 5722-PG101-R
296). Broadcom recommends the settings shown in
Bro adco m Co rp or atio n
Recommended Value
150
150
and "Send Max Coalesced BD Count (Offset 0x3C14)"
Recommended Value
10
10
Table

Settings

Recommended Value
0
0
297), which is the location where the MAC
282).
245).
"Ethernet MAC Mode Register (Offset 0x400)" on
"Miscellaneous Local Control Register (Offset 0x6808)"
"Interrupt Mailbox 0 Register (Offset 0x200–0x207)" on
BCM5722
and "Send Max Coalesced BD Count
40.
291).
Initialization Page 88