Broadcom BCM5722 Programmer's Manual page 153

Programmer's Guide
10/15/07
R RISC P
ESET ROCESSOR
The RX processor can be reset by setting the Reset RX RISC Bit of the RX RISC Mode register (see
Register (Offset 0x5000)" on page
completed.
For example, to reset RX RISC, do the following:
WR 5004, 0xffffffff /* Clear all CPU state */
WR 0x5000, 0x1
Wait until Bit 0 of register at 0x5000 is cleared.
H RISC P
ALT ROCEDURE
1. Clear the RX RISC state register. Write 0xFFFFFFFF to the RX_RISC_State register (see
(Offset 0x5004)" on page
2. Issue RX RISC halt. Write the RISC_MODE_HALT bit to the RX_RISC_Mode register (see
(Offset 0x5000)" on page
3. Read/verify that the RISC_MODE_HALT bit is set. Read the Rx RISC_MODE_HALT bit back from the RX_RISC_Mode
register. Break from procedure if bit is set.
4. Delay 10 µs and jump to step 1. Repeat the procedure up to 10,000 times.
S RISC P
TART ROCEDURE
This procedure first stops the RX RISC and modifies the program counter. The RISC processor is then started to begin
executing firmware at new address given by program counter.
1. Clear the RX RISC state register. Write 0xFFFFFFFF to the RX_RISC_State register (see
(Offset 0x5004)" on page
2. Set the RX RISC program counter. Write t3FwTextAddr to the RX_RISC_PC register
(Offset 0x501C)" on page
Note: The t3FwTextAddr should not be converted to a register relative address. The RISCs execute from
a local memory space. The conversion is only necessary for writing t3FwText [] to the scratch pad using
register space—the host view of the scratch pad region is different from the RISC view. See
page 93.
3. Read back the PC register. Read the RX_RISC_PC register and verify that t3FwTextAddr is set. If properly set, then
jump to Step 7.
4. Clear the RX RISC state register. Write 0xFFFFFFFF to the RX_RISC_State register.
5. Halt the RX RISC. Write the RISC_MODE_HALT bit to the RX_RISC_Mode register.
6. Delay one millisecond. Jump to
7. Clear the RX RISC state register. Write 0xFFFFFFFF to the RX_RISC_State register.
8. Clear the RX RISC mode register. Write 0x00 to the RX_RISC_Mode register (see
0x501C)" on page 320).
Document 5722-PG101-R
317). This bit is self-clearing bit; it will be cleared once internal reset of processor is
318).
317).
318).
320).
Step 2. and repeat procedure.
Bro adco m Co rp or atio n
BCM5722
"RX RISC Mode
"RX RISC State Register
"RX RISC Mode Register
"RX RISC State Register
(see"RX RISC Program Counter
Table 41 on
"RX RISC Program Counter (Offset
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