Broadcom BCM5722 Programmer's Manual page 469

Programmer's Guide
10/15/07
Bit Field
16 Disable Error Recovery
(BCM5787,
BCM5787M,
BCM5754,
BCM5754M,
BCM5906, BCM5906M
devices only)
Reserved (other
devices)
11 Enable Immediate L1
Exit Issue Fix (CQ9901
Fix) (BCM5722,
BCM5755,
BCM5755M,
BCM5756M, BCM5757
only)
Reserved (other
devices)
10 Reserved
9 Enable x16 Slot L1
Entry Fix (CQ9535 Fix)
(BCM5722, BCM5755,
BCM5755M,
BCM5756M, BCM5757
only)
Reserved (other
devices)
8 Enable Electrical
Ordered Set Not
Detected Fix (CQ9413
Fix) (BCM5722,
BCM5755,
BCM5755M,
BCM5756M, BCM5757
only)
Reserved (other
devices)
7 Reserved
6 PCIe 1.0 Mode
5 PCIe 1.0 Scrambler
Document 5722-PG101-R
Table 472: PHY Test Control Register (Offset 0x7E2C) (Cont.)
Description
1 = When receive error exceeds programmed threshold,
cause CPU attention only.
0 = When receive error exceeds programmed threshold,
automatically cause recovery and re-train the link interface.
Enable the immediate L1 Exit Fix
• 0 = Disable Fix
• 1 = Enable Fix
Note: Refer to E1_5751B0_09901 in the 5751-ES4xx-R
Errata for details.
–
Enable the x16 Slot L1 Entry problem Fix
• 0 = Disable Fix
• 1 = Enable Fix
Enable this bit to avoid possible premature exit from the L1
state to recovery state.
Enable the Electrical Ordered Set not Detected Fix
• 0 = Disable Fix
• 1 = Enable Fix
The BCM5751/BCM5721 receiver fails to detect an electrical
idle ordered set if it is sent after a partially completed DLLP or
TLP. This causes the link training state machine to see an
unexpected electrical idle and transition to the recovery state
instead of the L0s, L1, or L2 state. Set this bit to 1 to fix the
above problem.
Should not be written with a value other than default value
read from this bit.
When this bit is:
• Set to 1, the physical layer LTSSM state machine operates
in PCIe 1.0 mode.
• Clear, it operates in PCIe 1.0a mode.
When this bit is:
• Set to 1, the PCIe scrambler operates in PCIe 1.0 mode.
• Clear, it operates in PCIe 1.0a mode.
Bro adco m Co rp or atio n
BCM5722
Init Access
0 RW
0 RO
0 R/W
0 RO
0 R/W
0 R/W
0 RO
0 R/W
0 RO
0 R/W
0 R/W
0 R/W
PCIe Registers Page 410