Table 512: Auxiliary Control Register (Phy_Addr = 0X1, Reg_Addr = 18H, Shadow = 111, Misc Control) - Broadcom BCM5722 Programmer's Manual

BCM5722
A C
UXILIARY ONTROL
M C )
ISC ONTROL

Table 512: Auxiliary Control Register (PHY_Addr = 0x1, Reg_Addr = 18h, Shadow = 111, Misc Control)

Bit Field
15 Write Enable (Bits 11:3) • 1 = Write bits 14:0.
14:12 Shadow Register Read
Selector
11 Packet Counter Mode • 1 = Receive packet counter.
10 Reserved
9 Force Auto-MDIX Mode • 1 = Auto-MDIX is enabled when auto-negotiation is
8 RGMII Timing Mode
7 RGMII Mode
6 RGMII RXER Mode
5 RGMII Out Of Band
Status Disable
4 Reserved
3 MDIO All PHY Select
2:0 Shadow Register
Select
Page 449 Transceiver Registers
R (PHY_A
EGISTER DDR
Description
• 0 = Write bits 14:12 and 2:0.
• 000 = Normal Operation
• 001 = 10 BASE-T Register.
• 010 = Power Control Register
• 011 = Reserved.
• 100 = Misc Test Register 1
• 101 = Misc Test Register 2
• 110 = Reserved.
• 111 = Misc Control Register
• 0 = Transmit packet counter.
–
disabled.
• 0 = Auto-MDIX is disabled when auto-negotiation is
disabled.
• 1 = RGMII RXC delayed timing mode.
• 0 = RGMII RXC/RXD aligned timing mode.
N/A
N/A
• 1 = Send regular data during IPG.
• 0 = Send Out-Of-Band Status info in RGMII mode.
• 1 = All PHY selected during MDIO writes when PHY
address = 00000b.
• 0 = Normal operation.
The Auxiliary Control Register provides access to eight
registers using a shadow technique. These three bits written
define which set of 13 upper bits are used. No setup is
required. Register reads are determined by the previous write
operation.
• 000 = Normal Operation
• 001 = 10 BASE-T Register.
• 010 = Power Control Register
• 011 = Reserved.
• 100 = Misc Test Register 1
• 101 = Misc Test Register 2
• 110 = Reserved.
• 111 = Misc Control Register
Bro adco m C orp or atio n
= 0 1, R _A = 18
X EG DDR
Programmer's Guide
10/15/07
, S = 111,
H HADOW
Init Access
0 R/W SC
000 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
1 R/W
0 R/W
000 R/W
Document 5722-PG101-R