Receive Max Coalesced Bd Count During Interrupt (Offset 0X3C20); Send Max Coalesced Bd Count During Interrupt (Offset 0X3C24); Status Block Host Address Register (Offset 0X3C38); Status Block Base Address Register (Offset 0X3C44) - Broadcom BCM5722 Programmer's Manual

BCM5722
R M C
ECEIVE AX OALESCED
This register is similar to "Receive Max Coalesced BD Count (Offset 0x3C10)" on page
host is considered to be in its interrupt service routine (ISR). In this case, the NIC considers the host to be in its ISR whenever
"Interrupt Mailbox 0 Register (Offset 0x200–0x207)" on page
or the Mask Interrupt bit is set.
S M C
END AX OALESCED
This register is similar to "Send Max Coalesced BD Count (Offset 0x3C14)" on page
when the host is considered to be in its ISR. In this case, the NIC considers the host to be in its ISR whenever
Mailbox 0 Register (Offset 0x200–0x207)" on page 238
the Mask Interrupt bit is set.
S B H
TATUS LOCK OST
This 64-bit register is in host address format and tells the NIC where to DMA the status block.
S B B
TATUS LOCK ASE
This 32-bit register is the location of the status block structure in NIC memory.
F A R
LOW TTENTION
The Flow attention register reports attentions from the various transmit and receive state machines, flow-through queues
and the MBUF allocator. Whenever one of these blocks detects an attention situation, it sets the appropriate bit in the Flow
attention register. Refer to the state machine causing the attention to determine the exact cause. The attention bits are
cleared by writing a one to the bit (W2C). If a bit is marked as fatal, it means that the associated state machine is halted, and
that corrective action must be taken by a CPU.
Bit Field
31 Send BD Initiator
30 Send BD Completion
29 Send BD Ring Selector
28 Send Data Initiator
27 Send Data Completion
26:24 Reserved
23 Recv BD Initiator
22 Recv BD Completion
21 Recv List Placement
Page 297 Host Coalescing Control Registers
BD C D
OUNT
BD C D
OUNT URING
A R
DDRESS EGISTER
A R
DDRESS EGISTER
(O 0
EGISTER FFSET X

Table 286: Flow Attention Register (Offset 0x3C48)

Description
The Send BD Initiator state machine has caused an attention.
The Send BD Completion state machine has caused an
attention.
The Send BD Ring Selector state machine has caused an
attention.
The Send Data Initiator state machine has caused an
attention.
The Send Data Completion state machine has caused an
attention.
–
The Recv BD Initiator state machine has caused an attention.
The Recv BD Completion state machine has caused an
attention.
The Recv List Placement state machine has caused an
attention.
Bro adco m C orp or atio n
I (O
URING NTERRUPT
238" for host standard and flat modes is set to a nonzero value,
I (O
NTERRUPT FFSET
for host standard and flat modes is set to a nonzero value, or when
(O 0 3C38)
FFSET X
(O 0 3C44)
FFSET X
3C48)
Programmer's Guide
0 3C20)
FFSET X
296, but it is used instead when the
0 3C24)
X
296, but this register is used instead
Init
0
Document 5722-PG101-R
10/15/07
"Interrupt
Fatality
Fatal
Fatal
Fatal
Fatal
Fatal
Fatal
Fatal
Fatal
Fatal