Revision Levels; Table 3: Family Revision Levels - Broadcom BCM5722 Programmer's Manual

Programmer's Guide
10/15/07
R L
EVISION EVELS
See Table 3 for the revision levels of the BCM5722 Ethernet controllers. Host software can use the PCI Revision ID and
Chip ID information in the PCI configuration registers to determine the revision level of the BCM5722 Ethernet controller on
the board, and then load the appropriate workaround described in the errata sheets.
The Broadcom PCI vendor ID is 0x14E4.
by firmware in accordance with the manufacturing information supplied in NVRAM (see
for more details).
Device
Family
a
Member
ID
BCM5722 0x165A
BCM5755 0x167B
0x167B
BCM5755M 0x1673
0x1673
BCM5754 0x167A
0x167A
BCM5754M 0x1672
0x1672
BCM5756M 0x1674
BCM5757 0x1670
BCM5786 0x169A
BCM5787 0x169B
0x169B
0x169B
BCM5787M 0x1693
0x1693
0x1693
BCM5906 0x1712
0x1712
0x1712
BCM5906M 0x1713
0x1713
0x1713
a. See "Device ID Register (Offset 0x02)" on page
b. See "Revision ID Register (Offset 0x08)" on page 191
firmware programs this register with the value as given in the table.
c. See "Miscellaneous Host Control Register (Offset 0x68)" on page
id.
d. See the appropriate errata documentation for the errata information and resolutions.
Document 5722-PG101-R
Table 3 shows the default values of PCI device IDs. These values may be modified

Table 3: Family Revision Levels

PCI
Revision
Chip ID
b
Level
Revision ID
A0 0x00 0xA000xxxx
A0 0x00 0xA000xxxx
A1 0x01 0xA001xxxx
A0 0x00 0xA000xxxx
A1 0x01 0xA001xxxx
A0 0x00 0xB000xxxx
A1 0x01 0xB001xxxx
A0 0x00 0xB000xxxx
A1 0x01 0xB001xxxx
A0 0x00 0xA000xxxx
A0 0x00 0xA000xxxx
A2 0x02 0xB000xxxx
A0 0x00 0xB000xxxx
A1 0x01 0xB001xxxx
A2 0x02 0xB002xxxx
A0 0x00 0xB000xxxx
A1 0x01 0xB001xxxx
A2 0x02 0xB002xxxx
A0 0x00 0xC000xxxx
A1 0x01 0xC001xxxx
A2 0x02 0xC002xxxx
A0 0x00 0xC000xxxx
A1 0x01 0xC001xxxx
A2 0x02 0xC002xxxx
189.
Bro adco m Co rp or atio n
c
PHY core
BCM5482_gphy_core
BCM5482_gphy_core
BCM5482_gphy_core
BCM5482_gphy_core
BCM5482_gphy_core
BCM5482_gphy_core
BCM5482_gphy_core
BCM5482_gphy_core
BCM5482_gphy_core
BCM5482_gphy_core
BCM5482_gphy_core
BCM5482_gphy_core
BCM5482_gphy_core
BCM5482_gphy_core
BCM5482_gphy_core
BCM5482_gphy_core
BCM5482_gphy_core
BCM5482_gphy_core
s_ephy_core_top_cr_cup(A3 patch 3) TBD
s_ephy_core_top_cr_cup(A3 patch 3) TBD
s_ephy_core_top_cr_cup(A3 patch 3) TBD
s_ephy_core_top_cr_cup(A3 patch 3) TBD
s_ephy_core_top_cr_cup(A3 patch 3) TBD
s_ephy_core_top_cr_cup(A3 patch 3) TBD
The hardware default value of this register is 0x00. The bootcode
204. The lower 16 bits are don't cares for determining chip
BCM5722
"NVRAM Configuration" on page 41
Errata Sheet
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD

Revision Levels

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