Table 131: Memory Window Base Address Register (Offset 0X7C) - Broadcom BCM5722 Programmer's Manual

Programmer's Guide
10/15/07
M W B
EMORY INDOW
The Memory Window Base Address register defines the device local memory address which is to be the base address for
the 32 KB memory window provided by the BCM5722 Ethernet controller. This register may contain any valid local memory
address, but the usage of the least significant 15 bits varies depending on how the local memory is to be accessed. If the 32
KB memory window is used, then the least significant 15 bits are ignored. If the Memory Window Data register is referenced,
then the entire Memory Window Base Address register is used to indicate the specific local memory address of the operation.
To use the Memory Window Base Address/Memory Window Data registers:
1. Enable indirect mode by setting the Enable Indirect Access bit of the Miscellaneous Host Control register (see
"Miscellaneous Host Control Register (Offset 0x68)" on page
2. Write the address of the Memory location that you would like to access to the Memory Window Base Address register
(offset 0x7C–0x7F).
The least significant two bits of the Memory Window Base Address register will always be ignored. Additionally, if the
access to Memory is a 64-bit PCI access, the least significant three bits will be ignored, since Memory is naturally double
word (64-bit) aligned. To allow access to all of the BCM5722 Ethernet controller memory, the range of the Memory
Window Base Address register is [23:2]. Also note that Target Word Swap applies to Memory accesses. This needs to
be taken into account when reading or writing from the Memory Window Data register.
3. To write to the Memory location pointed to by the Memory Window Base Address register, write the 32-bit or 64-bit data
to the Memory Window Data register.
A 64-bit write to the Memory Window Data register can only occur when using a PCI Memory command and not a PCI
Config command. PCI Config commands only allow for 32-bit data transfers. Also note that the particular bytes that are
to be written must have their associated byte enables set. At least one byte enable in the word(s) to be written from the
PCI-based Host must be asserted for the write to occur, otherwise, the write will be ignored.
4. To read the Memory location pointed to by the Memory Window Base Address register, read the 32-bit or 64-bit data
from the Memory Window Data register.
The value that is written to the Memory Window Base Address register is also used for the 32-KB Memory Window. The
offset of the Memory Window into the Memory space can be determined by zeroing Memory Window Base Address
register bits[14:0].
Bit Field
31:24 Reserved
23:2 Memory Window Base
Addr
1:0 Reserved
Document 5722-PG101-R
A R
ASE DDRESS EGISTER

Table 131: Memory Window Base Address Register (Offset 0x7C)

Description
–
Local controller memory address of the NIC memory
region that can be accessed via Memory Window Data
register.
–
Bro adco m Co rp or atio n
(O 0 7C)
FFSET X
204).
Broadcom Vendor-Specific Capabilities
BCM5722
Init Access
0 RO
0 on hard R/W
reset
0 RO
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