Table 354: Rx Cpu Event Enable Register (Offset 0X684C)-Bcm5722, Bcm5755, Bcm5755M, Bcm5756M, Bcm5757, Bcm5754, Bcm5787 Only - Broadcom BCM5722 Programmer's Manual

BCM5722
RX CPU E E
VENT NABLE
Setting a bit in this register enables an interrupt to the CPU or the event.
Table 354: RX CPU Event Enable Register (Offset 0x684C)—BCM5722, BCM5755, BCM5755M, BCM5756M,
Bit Field
31 Flash
30 VPD
29 Timer Reference
Reached
28 ROM
27 HC module
26 RX CPU module
25 EMAC module
24 Memory Map Enable Bit Set by HW, cleared by SW.
23 Reserved
22 High-Priority Mail Box
21 Low-Priority Mail Box
20 DMA
19 Reserved
18–17 Reserved
16 ASF Location 15
15 TPM Interrupt Enable
14 ASF Location 14
13 Reserved
12 ASF Location 13
11 Unused SDI
10 SDC (Post TCP
segmentation)
9 SDI (Pre TCP
segmentation)
8 RDIQ FTQ (Received an
ASF)
7 ASF Location 12
6 Reserved
5 ASF Location 11
4 Reserved
3 ASF Location 10
2 Reserved
1 ASF Location 9
0 ASF Location 8
Page 343 General Control Registers
R (O
EGISTER FFSET
BCM5757, BCM5754, BCM5787 Only
Description
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Bro adco m C orp or atio n
0 684C)
X
Programmer's Guide
10/15/07
Init Access
0 RO
0 RO
0 R/W
0 RO
0 RO
0 RO
0 RO
0 R/W
0 R/W
0 RO
0 RO
0 RO
0 R/W
00 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 RO
0 RO
0 RO
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Document 5722-PG101-R