Table 414: Transaction Configuration Register (0X7C04) - Broadcom BCM5722 Programmer's Manual

Programmer's Guide
10/15/07
Bit Field
20 Disable UR Error
19 Disable RSV Error
18 Enable MPS Check
17 Disable EP Error
16 Enable Bytecount Check
15:14 Reserved
13:11 DMA Read Traffic Class
10:8 DMA Write Traffic Class
7:6 Reserved
5:0 Completion Timeout
T C
RANSACTION ONFIGURATION
Bit Field
31 Enable_Retry_Buffer_Timing_Mod
30 Reserved
29 Enable 1-shot MSI (BCM5906 only) Write "1" to this bit to enable 1-shot MSI. If
Reserved (all others)
28 Reserved
Document 5722-PG101-R
Table 413: TLP Control Register (Offset 0x7C00) (Cont.)
Description
When clear, this bit enables the DMA completion logic to check
for a completion packet with an Unsupported Request value.
When clear, this bit enables the DMA completion logic to check
for a completion packet with a Reserved value.
When set, this bit enables the DMA completion logic to check for
a TLP that violates the Maximum Payload Size requirement.
When clear, this bit enables the Transaction Layer to check for
Data Poisoning.
When set, this bit enables the Transaction Layer's target to check
for byte count errors on incoming target accesses.
–
DMA Read Traffic Class.
DMA Write Traffic Class.
–
Programmable completion timeout in milliseconds.
R (0
EGISTER

Table 414: Transaction Configuration Register (0x7C04)

Description
Allows the Retry Buffer RAM Timing
Parameter to be modified if process timing
model was incorrect.
• 0 = Disable
• 1 = Enable new timing mode
–
one-shot MSI mode is enabled, the device
automatically disables all future interrupts and
goes into "during-interrupt" coalescing mode
after an MSI is generated. This is possible
because MSI is an edge-triggered interrupt
that does not require de-assertion by
software. Enabling one-shot MSI mode
reduces the overhead of the driver writing to
the interrupt mailbox in the interrupt handler.
The Interrupt is re-enabled in the normal way
by software writing to the interrupt mailbox.
–
–
Bro adco m Co rp or atio n
7C04)
X
BCM5722
Init Access
0 R/W
0 R/W
1 R/W
0 R/W
1 R/W
0 R/W
0x0 R/W
0x0 R/W
0x0 R/W
0x2f R/W
Access Reset Init
RW Core 0
RW Core 0
RW Core 0
RW Core 0
PCIe Registers Page 384