Table 494: Receiver Not_Ok Counters (Phy_Addr = 0X1, Reg_Addr = 14H, Normal Operation); Table 495: Receiver Not_Ok Counters (Phy_Addr = 0X1, Reg_Addr = 14H, Crc Error Count Operation) - Broadcom BCM5722 Programmer's Manual

BCM5722
R NOT_OK C
ECEIVER
Normal Operation (CRC Count Visibility = 0)
These counters increment each time the local or remote receiver enters the NOT_OK state (freezes at the maximum value
FFh) when the CRC Error Count Visibility bit of PHY Test Register 1 (see
REG_Addr = 1EH)" on page

Table 494: Receiver NOT_OK Counters (PHY_Addr = 0x1, Reg_Addr = 14h, Normal Operation)

Bit Field
15:8 Local Receiver
NOT_OK Counter
7:0 Remote Receiver
NOT_OK Counter
CRC Error Count Operation (CRC Count Visibility = 1)
The CRC error counter is merged into a 16-bit counter and increments each time the MAC Transceiver detects a CRC error
when the CRC Error Count Visibility bit of PHY Test Register 1 (see
1EH)" on page 480) is set. This counter freezes at the maximum value FFFFh. The counter automatically clears when read.

Table 495: Receiver NOT_OK Counters (PHY_Addr = 0x1, Reg_Addr = 14h, CRC Error Count Operation)

Bit Field
15:0 CRC Error Counter
E R
XPANSION EGISTER
When the "Expansion Register Access Register (PHY_ADDR = 0x1, Reg_Addr = 17h)" on page 434
allows read/write access to the Expansion Register selected in the Expansion Register Access Register.
Page 433 Transceiver Registers
(PHY_A
OUNTERS
480) is clear. The counters automatically clear when read.
Description
Number of times local receiver was not OK since last
read (when PHY Test Register 1.
CRC_Error_Count_Visibility bit (see
1 (PHY_Addr = 0X1, REG_Addr = 1EH)" on page
clear).
Number of times the BCM5722 Ethernet controller
detected that the remote receiver was not OK since last
read (when PHY Test Register 1.
CRC_Error_Count_Visibility bit (see
1 (PHY_Addr = 0X1, REG_Addr = 1EH)" on page
clear).
Description
This register becomes a 16-bit CRC error counter when
PHY Test Register 1.CRC_Error_Count_Visibility bit (see
"PHY Test Register 1 (PHY_Addr = 0X1, REG_Addr =
1EH)" on page 480) is set.
A D (PHY_ADDR = 01
CCESS ATA
Bro adco m C orp or atio n
= 0 1, R _A
DDR X EG DDR
"PHY Test Register 1 (PHY_Addr = 0X1,
"PHY Test Register
"PHY Test Register
"PHY Test Register 1 (PHY_Addr = 0X1, REG_Addr =
, REG_ADDR = 15
H
Programmer's Guide
= 14 )
H
Init Access
00h R/W
480) is
00h R/W
480) is
Init Access
0000h R/W
)
H
is enabled, this register
Document 5722-PG101-R
10/15/07