Table 461: Phy Mode Register (Offset 0X7E00); Table 462: Phy/Link Status Register (Offset 0X7E04) - Broadcom BCM5722 Programmer's Manual

BCM5722
Bit Field
2 dASPM10usTimer
1 dFFU_EL1
0 dFlowCtlUpdate1_1
PHY M R
ODE EGISTER
Bit Field
31:2 Reserved
1 Link disable
0 Soft reset
PHY/L S R
INK TATUS
Bit Field
31:8 Reserved
7 Link partner request
loopback
6 Link partner disable
scrambler
5 Extended Synch
4 Polarity inverted
3 Link Up
2 Link training
1 Receive data valid
0
Page 405 PCIe Registers
Table 460: Link PCIe 1.1 Control Register (0x7D54) (Cont.)
Description
Disable ASPM 10us Timer before next ASPM
L1 request after naked ASPM L1 request. This
is a PCIe1.1 requirement. Assertion of disable
will go back to 1.0a version.
Disable fast flow control update on exit of L1.
This is a PCIe1.1 requirement. If disable is
asserted, will go back to 1.0a version.
Disable PCIe 1.1 flow control update rate of
34us. If disable is asserted, will go back to the
1.0a version with 44us update rate.
(O 0 7E00)
FFSET X

Table 461: PHY Mode Register (Offset 0x7E00)

Description
Write as 0, ignore when read.
Disable the logical PHY layer functions.
Softreset to the phylogical block. This bit will be self-
cleared after four clock cycles.
(O 0
EGISTER FFSET X

Table 462: PHY/Link Status Register (Offset 0x7E04)

Description
–
Link partner requested remote loopback mode during
training process.
The link partner disabled the scrambler during training
process.
Extended synchronization from PCI configuration
register. If set, 4K FTS ordered sets must be sent during
link recovery.
Lane polarity is inverted.
The link training process is completed and link is ready
for use.
The link is in the training process.
Symbol synchronization is achieved and receive data is
valid
–
Bro adco m C orp or atio n
7E04)
Programmer's Guide
Init Reset Access
0 Chip RW
(hard +
soft)
0 Chip RW
(hard +
soft)
0 Chip RW
(hard +
soft)
Init Access
0 RO
0 R/W
0 R/W
Init Access
0 RO
0 RO
0 RO
0 RO
0 RO
0 RO
0 RO
0 RO
Document 5722-PG101-R
10/15/07