Table 55: Power Management Registers - Broadcom BCM5722 Programmer's Manual

BCM5722
R Q C
EGISTER UICK ROSS
The BCM5722 Ethernet controller power management registers are listed in
Register Bit
Misc Local Control Misc_Pin_0_Output
Misc Local Control Misc_Pin_0_Output_Enable
Misc Local Control Misc_Pin_1_Output
Misc Local Control Misc_Pin_1_Output_Enable
Misc Local Control Misc_Pin_2_Output
Misc Local Control Misc_Pin_2_Output_Enable
Misc Host Control Enable_Clock_Control_Register
PCI Clock_Control TX RISC_Clock_Disable
PCI Clock_Control RX RISC_Clock_Disable
PCI Clock_Control Select_Alternate_Clock
PCI Clock_Control PLL133
PCI Power PME_Enable
Management
Control/Status
PCI Power Power_State
Management
Control/Status
Page 141 Power Management
R
EFERENCE

Table 55: Power Management Registers

Description
GPIO pin 0
When asserted, MAC drives
pin output
GPIO pin 1
When asserted, MAC drives
pin output
GPIO pin 2
When asserted, MAC drives
pin output
Disable the clock to the
transmit CPU
Disable the clock to the
receive CPU
Use an alternate clock as a
reference, rather than the PLL
133
Disable the 133-MHz phased
locked loop
–
–
Bro adco m C orp or atio n
Programmer's Guide
Table 55.
Cross Reference
"Miscellaneous Local Control
Register (Offset 0x6808)" on
page 336.
"PCI Clock Control Register
(Offset 0x74)" on page
"Power Management Control/
Status Register (Offset 0x4C)" on
page 198.
Document 5722-PG101-R
10/15/07
207.