Table 473: Phy/Serdes Control Override Register (Offset 0X7E30) - Broadcom BCM5722 Programmer's Manual

BCM5722
Bit Field
4 Fast Symbol Lock Up
3 Down Stream Lane
2 Training Bypass
1 External Loopback
0 Internal Loopback
PHY/S D C
ER ES ONTROL

Table 473: PHY/SerDes Control Override Register (Offset 0x7E30)

Bit Field
31:18 Reserved
17 obsvElecIdleValue
16 obsvElecIdleOverride
15 pllIsUpValue
14 pllIsUpOverride
13 rcvrDetValue
12 rcvrDetOverride
11:10 rcvrDetTimeControl
9:0 rcvrDetectionTime
Page 411 PCIe Registers
Table 472: PHY Test Control Register (Offset 0x7E2C) (Cont.)
Description
When this bit is:
• Set to 1, the symbol boundary locks after receiving the first
COM symbol.
• Clear, the symbol boundary locks after receiving four COM
symbols within a 64-symbol time.
Set this bit to change the link to be a downstream lane (or
upstream component).
Set to bypass link initialization and configuration process.
Force remote (external) loopback test mode.
Force internal parallel loopback test mode.
O R
VERRIDE EGISTER
Description
Override value for the obsvElecIdle signal from SerDes.
Set to override the obsvElecIdle signal value from SerDes with the
value in bit 17 of this register.
Override value for pllIsUp signal form SerDes.
Set to override the pllisUp signal value from SerDes with the value in
bit 15 of this register.
Override value for rcvrDetected signal from SerDes.
Set to override the rcvrDetected signal from SerDes with the value in
bit 13 of this register.
Time unit of the rcvrDetectionTime:
• 2'b00 = Symbol time.
• 2'b01 = 64 ns.
• 2'b10 = 1 µs.
Time value that the PHY logical layer uses for timing receiver detection
sequences.
Bro adco m C orp or atio n
(O 0 7E30)
FFSET X
Programmer's Guide
10/15/07
Init Access
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Init Access
0 RO
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0x0 R/W
0x3FF R/W
Document 5722-PG101-R