Table 225: Send Data Initiator Mode Register (Offset 0X0C00)-Bcm5722, Bcm5755, Bcm5755M, Bcm5756M, Bcm5757, Bcm5754, Bcm5787 Only; Table 226: Send Data Initiator Mode Register (Offset 0X0C00)-Bcm590X Only - Broadcom BCM5722 Programmer's Manual

BCM5722
S D I
END ATA NITIATOR
BCM5755M, BCM5756M, BCM5757, BCM5754, BCM5787,
Table 225: Send Data Initiator Mode Register (Offset 0x0C00)—BCM5722, BCM5755, BCM5755M, BCM5756M,
Bit Field
31:5 Reserved
4 Pre-DMA Debug Enable
3 Hardware Pre-DMA Enable
2 Stats Overflow Attn Enable
1 Enable
0 Reset
S D I
END ATA NITIATOR
Table 226: Send Data Initiator Mode Register (Offset 0x0C00)—BCM590X Only
Bit Field
31:8 Reserved
7 dec_1ms
6 inc_64us
5 inc_4us
4 inc_512ns
3 Hardware Pre-DMA Enable
2 Stats Overflow Attn Enable
1 Enable
0 Reset
a. Bits 7:4 can be set simultaneously. Software must poll these bits to ensure that they are all 0's before setting any of these bits.
Page 269 Send Data Initiator Control Registers
M R (O
ODE EGISTER
BCM5757, BCM5754, BCM5787 Only
Description
–
When this bit is set, the Send Data Initiator state machine
is halted when the pre-DMA bit of the Send BD is set.
Enable hardware LSO pre-DMA processing
Enable attention for statistics overflow
This bit controls whether the Send Data Initiator state
machine is active or not. When set to 0, it completes the
current operation and cleanly halts. Until it is completely
halted, it remains 1 when read.
When this bit is set to 1, the Send Data Initiator state
machine is reset. This is a self-clearing bit.
M R (O
ODE EGISTER
Description
–
When set, the timer at 0xc24 is decremented by
0x100000. When done, the bit is cleared by hardware.
This bit may stay high for as long as 1 ms before it gets
a
cleared.
When set, the timer at 0xc24 is incremented by 0x10000.
When done, the bit is cleared by hardware.
When set, timer at 0xc24 is incremented by 0x1000.
When done, the bit is cleared by hardware.
When set, the timer at 0xc24 is incremented by 0x100.
When done, the bit is cleared by hardware.
Enable hardware LSO pre-DMA processing
Enable attention for statistics overflow
This bit controls whether the Send Data Initiator state
machine is active or not. When set to 0, it completes the
current operation and cleanly halts. Until it is completely
halted, it remains 1 when read.
When this bit is set to 1, the Send Data Initiator state
machine is reset. This is a self-clearing bit.
Bro adco m C orp or atio n
0 0C00)—BCM5722, BCM5755,
FFSET X
0 0C00)—BCM5907 O
FFSET X
Programmer's Guide
BCM5906 O
AND NLY
Init Access
0 RO
0 R/W
0 R/W
0 R/W
1 R/W
0 R/W
NLY
Init Access
0 RO
0 R/W
0 R/W
a
0 R/W
0 R/W
a
0 R/W
0 R/W
1 R/W
0 R/W
Document 5722-PG101-R
10/15/07