BCM5722
M
R
ANAGEMENT OF
Status Block
The host software manages the producer rings through the Mailbox registers and by using the status block. It does this by
writing to the Mail Box registers when a BD is available to DMA to the BCM5722 Ethernet controller and reading the status
block to see how many BDs have been consumed by the BCM5722 Ethernet controller. The status block can be seen in
"Status Block" on page
53.
The status block is controlled and updated by the BCM5722 Ethernet controller. The status block in host memory is
constantly updated through a DMA copy by the BCM5722 Ethernet controller from an internal status block. The updates
occur at specific intervals and host coalescence conditions that are specified by host software during initialization of the
BCM5722 Ethernet controller. The registers for setting the intervals and conditions are in the Host Coalescing Control
registers (see
"Host Coalescing" on page
an updated status block to the 32-bit address that is set by the host software in the Host Coalescing Control registers,
0x3c38.
Among other status, the status block displays the last 16-bit value, BD index that was DMAed to the BCM5722 Ethernet
controller from receive producer ring. The BCM5722 Ethernet controller updates these indices as the recipient or consumer
of the BD from the producer rings.
Mailbox
The host software is responsible for writing to the Mailbox registers (see
the producer rings for use by the BCM5722 Ethernet controller. Host software should use the high-priority mailbox region
from 0x200– 0x3FF for host standard and flat modes and the low-priority mailbox region from 0x5800–0x59FF for indirect
register access mode.
The Mailbox registers (starting at memory offset 0x200 for host standard and flat modes and offset 0x5800 for indirect mode)
contain the following receive producer index register.
Receive BD Producer Ring Producer Index
•
Host standard and flat modes: memory offset 0x268–0x26F
•
Indirect mode: memory offset 0x5868–0x586F
Page 63
Receive Producer Ring
P
R
X
RODUCER
INGS WITH
177) starting at memory offset 0x3c00. The BCM5722 Ethernet controller DMAs
Bro adco m C orp or atio n
M
R
AILBOX
EGISTERS AND
Figure 26 on page
Programmer's Guide
10/15/07
S
B
TATUS
LOCK
64) when a BD is available from
Document 5722-PG101-R
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