Table 336: Message Signaled Registers; Table 337: Msi Mode Register (Offset 0X6000); Table 338: Msi Status Register (Offset 0X6004) - Broadcom BCM5722 Programmer's Manual

Programmer's Guide
10/15/07
M S
ESSAGE IGNALED
Offset
0x6000–0x6003
0x6004–0x6007
0x6008–0x600b
0x600C–0x67FF
MSI M R
ODE EGISTER
Bit Field
31:7 Reserved
6 MSI FIFO Overrun Attn MSI FIFO overrun attention enable.
5 MSI FIFO Underrun
Attn
4 PCI Parity Error Attn
3 PCI Master Abort Attn PCI master abort attention enable.
2 PCI Target Abort Attn
1 Enable
0 Reset
MSI S R
TATUS EGISTER
Bit Field
31:7 Reserved
6 MSI FIFO Overrun
5 MSI FIFO Underrun
4 PCI Parity Error
3 PCI Master Abort
2 PCI Target Abort
1:0 Reserved
Document 5722-PG101-R
I
NTERRUPT

Table 336: Message Signaled Registers

Registers
MSI Mode Register
MSI Status Register
MSI FIFO Access Register
Reserved
(O 0 6000)
FFSET X

Table 337: MSI Mode Register (Offset 0x6000)

Description
–
MSI FIFO underrun attention enable.
PCI parity error attention enable.
PCI target abort attention enable.
This bit controls whether the MSI state machine is active
or not. When set to 0, it completes the current operation
and cleanly halts. Until it is completely halted, it remains
one when read.
When this bit is set to 1, the MSI state machine is reset.
This is a self-clearing bit.
(O 0 6004)
FFSET X

Table 338: MSI Status Register (Offset 0x6004)

Description
–
MSI FIFO overrun status
MSI FIFO underrun status
PCI parity error status
PCI master abort status
PCI target abort status
–
Bro adco m Co rp or atio n
R
EGISTERS
Message Signaled Interrupt Registers
BCM5722
Init Access
0 RO
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
1 R/W
0 R/W
Init Access
0 RO
0 W2C
0 W2C
0 W2C
0 W2C
0 W2C
0 RO
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