Host Coalescing Mode Register (Offset 0X3C00) - Broadcom BCM5722 Programmer's Manual

Programmer's Guide
10/15/07
H C
OST OALESCING
Bit Field
31:13 Reserved
12 No Interrupt on Force
Update
11 No Interrupt on DMAD
Force
10 Clear Ticks Mode on
TX
Reserved (BCM5906
Only)
9 Clear Ticks Mode on
RX
8–7 Status Block Size
Reserved (BCM5906
Only)
6:4 MSI Bits
3 Coalesce Now
2 Attn_Enable
1 Enable
0 Reset
Document 5722-PG101-R
M R (O
ODE EGISTER
Table 284: Host Coalescing Mode Register (Offset 0x3C00)
Description
–
When set, writing the Coalesce Now bit will cause a
status block update without a corresponding interrupt
event.
When set, the COAL_NOW bit of the buffer descriptor
may be set to force a status block update without a
corresponding interrupt (see
on page 46).
When set, the TX Host Coalescing Tick counter initializes
to the idle state and begins counting only after a transmit
BD event is detected.
–
When set, the RX Host Coalescing Tick counter
initializes to the idle state and begins counting only after
a receive BD event is detected.
Status Block Size for partial status block updates (see
"Status Block" on page
• 00 = Full status block
• 01 = 64 byte
• 10 = 32 byte
• 11 = Undefined
–
The least significant MSI 16-bit word is overwritten by
these bits. Defaults to 0.
If set, Host Coalescing updates the Status Block
immediately and sends an interrupt to host. This is a self-
clearing bit. (For debug purpose only.)
When this bit is set to 1, an internal attention is generated
when an error occurs.
This bit controls whether the Host Coalescing state
machine is active or not. When set to 0, it completes the
current operation and cleanly halts. Until it is completely
halted, it remains one when read.
When this bit is set to 1, the Host Coalescing state
machine is reset. This is a self-clearing bit.
Bro adco m Co rp or atio n
0 3C00)
FFSET X
"Send Buffer Descriptors"
53):
Init
0
0
0
Host Coalescing Control Registers
BCM5722
Access
R/W
R/W
R/W
R/W
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Page 294