Table 52: Gpio Usage For Bcm5700/Bcm5701 Power Management For Broadcom Drivers; Table 53: Gpio Usage For Bcm5703C/Bcm5703S And Later Power Management For Broadcom Drivers; Table 54: Bcm5722 Ethernet Controller Power Pins - Broadcom BCM5722 Programmer's Manual

BCM5722
GPIO
The use of GPIO pins for power management is design-specific, though Broadcom-delivered drivers use GPIO pins in the
manner listed in Table 52 and
for a NIC design; it is not applicable to LAN-on-Motherboard (LOM) designs.

Table 52: GPIO Usage for BCM5700/BCM5701 Power Management for Broadcom Drivers

Function Description
VAux Switches the BCM5722 Ethernet controller to use VAux power

Table 53: GPIO Usage for BCM5703C/BCM5703S and Later Power Management for Broadcom Drivers

Function Description
VAux Sequence for switching to VAux
VMain Sequence for switching to VMain
a. x = Don't Care
P S D3 S
OWER UPPLY IN
Table 54 shows the power supply to various power pins on the BCM5722 Ethernet controller. This table assumes that host
software has switched power regulators using GPIO pins 0, 1, and 2.
Pin
VDD_CORE
VDD_IO
VDD_IO-PCI
C C
LOCK ONTROL
Certain functional blocks in the MAC architecture should be powered down before a transition to D3 ACPI state. MAC clock
generators/PLLs drive transistor level logic, which switch states on every clock pulse. Transistor level switching consumes
power (mW). Software should selectively disable clocking to non-essential functional blocks. Software must set the
Enable_Clock_Control_Register bit in the Miscellaneous Host Control register (see
(Offset 0x68)" on page 204); the assertion of this bit allows host software to configure the PCI clock control register. The
following clock bits should be configured in the PCI Clock Control register (see
on page 207):
RX RISC clock disable
•
• Select alternate clock—the 133-MHz PLL is not used as reference clock.
Page 139 Power Management
Table 53. This usage is only applicable when the BCM5722 Ethernet controller is configured
TATE

Table 54: BCM5722 Ethernet controller Power Pins

D3 Normal
PCI Slot
PCI Slot
PCI Slot
Bro adco m C orp or atio n
GPIO0
1
GPIO0
0
1
1
x
x
x
D3 Hot
Vaux
Vaux
PCI Slot
"Miscellaneous Host Control Register
"PCI Clock Control Register (Offset 0x74)"
Programmer's Guide
10/15/07
GPIO1 GPIO2
1 0
a
GPIO1 GPIO2
0 1
1 1
1 0
1 x
0 x
1 x
D3 Cold
Vaux
Vaux
No Power
Document 5722-PG101-R