Table 159: Correctable Error Status Register (Offset 0X110); Table 160: Correctable Error Mask Register (Offset 0X114); Table 161: Advanced Error Capabilities And Control Register (Offset 0X118) - Broadcom BCM5722 Programmer's Manual

BCM5722
C E
ORRECTABLE RROR
Bit Field
31:13 Reserved
12 Replay Timer Timeout
Status
11:9 Reserved
8 REPLAY_NUM
Rollover Status
7 Bad DLLP Status
6 Bad TLP Status
5:1 Reserved
0 Receiver Error Status
C E
ORRECTABLE RROR
Bit Field
31:14 Reserved
13 Advisory Non-Fatal
Error Mask
12 Replay Timer Timeout
Mask
11:9 Reserved
8 REPLAY_NUM
Rollover Mask
7 Bad DLLP Mask
6 Bad TLP Mask
5:1 Reserved
0 Receiver Error Mask
A E C
DVANCED RROR

Table 161: Advanced Error Capabilities and Control Register (Offset 0x118)

Bit Field
31:9 Reserved
8 ECRC Check Enable
7 ECRC Check Capable When this bit is set, it indicates that this device supports
6 ECRC Generation
Enable
5 ECRC Generation
Capable
Page 227 PCIe-Enhanced Capabilities
S R
TATUS EGISTER

Table 159: Correctable Error Status Register (Offset 0x110)

Description
–
This bit is set when a Replay Timer Timeout error occurs. 0
–
This bit is set when a REPLAY_NUM Rollover error
occurs.
This bit is set when a Bad DLLP error occurs.
This bit is set when a Bad TLP error occurs.
–
This bit is set when a Receiver error occurs.
M R (O
ASK EGISTER

Table 160: Correctable Error Mask Register (Offset 0x114)

Description
–
This bit is set by default to enable compatibility with
software that does not comprehend Role-Based Error
Reporting.
Setting this bit will mask Replay Timer Timeout errors.
–
Setting this bit will mask REPLAY_NUM Rollover errors.
Setting this bit will mask Bad DLLP errors.
Setting this bit will mask Bad TLP errors.
–
Setting this bit will mask Receiver errors.
C
APABILITIES AND ONTROL
Description
–
Setting this bit will enable ECRC checking.
ECRC Checking.
Setting this bit will enable ECRC generation.
When this bit is set, it indicates that this device supports
ECRC generation.
Bro adco m C orp or atio n
(O 0 110)
FFSET X
0 114)
FFSET X
R (O
EGISTER FFSET
Programmer's Guide
10/15/07
Init Access
0 RO
W2C
0 RO
0 W2C
0 W2C
0 W2C
0 RO
0 W2C
Init Access
0 RO
1 R/W
0 R/W
0 RO
0 R/W
0 R/W
0 R/W
0 RO
0 R/W
0 118)
X
Init Access
0 RO
0 R/W
1 RO
0 R/W
1 RO
Document 5722-PG101-R