Figure 17: Host Coalescing Engine - Broadcom BCM5722 Programmer's Manual

BCM5722
H C
OST OALESCING
H C
OST OALESCING
The Host Coalescing Engine is responsible for pacing the rate at which the NIC updates the send and receive ring indices
located in host memory space. The completion of a NIC update is reflected through an interrupt on the BCM5722 Ethernet
controller INTA pin or a Message Signalled Interrupt (MSI). Although update criteria are calculated separately, all updates
occur at once. This is because all of the ring indices are in one status block, and any host update updates all ring indices
simultaneously. The Host Coalescing Engine triggers based on a tick and/or a frame counter.
Status Buffer
Memory Manager
Page 33 Host Coalescing
E
NGINE
DMA
Write
Engine
Tick BD
Counter Counter
Host
Coalescing
Engine

Figure 17: Host Coalescing Engine

Bro adco m C orp or atio n
Programmer's Guide
Write
FIFO
PCIe
Interface
MSI
FIFO
I/O
Driver
Host software may
configure line IRQor MSI
10/15/07
Status Block
...
MSI
Mailbox
IRQ Host
Interrupt
Controller
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