Table 463: Phy/Link Ltssm Control Register (Offset 0X7E08); Table 464: Phy/Link Training Link Number (Offset 0X7E0C); Table 465: Phy/Link Training Lane Number (Offset 0X7E10) - Broadcom BCM5722 Programmer's Manual

Programmer's Guide
10/15/07
PHY/L LTSSM C
INK
Bit Field
31:8 Reserved
7 DisableScramble
6 DetectState
5 PollingState
4 ConfigState
3 RecovState
2 ExtLBState
1 ResetState
0 DisableState
PHY/L T
INK RAINING
Bit Field
31:8 Reserved
7:0 Lane Number
PHY/L T
INK RAINING
Bit Field
31:8 Reserved
7:0 Lane Number
Document 5722-PG101-R
R
ONTROL EGISTER

Table 463: PHY/Link LTSSM Control Register (Offset 0x7E08)

Description
–
Disable scrambling and de-scrambling.
High layer directs LTSSM to detect state if set. The bit is
cleared when LTSSM entered into detect state.
High layer directs LTSSM to Polling state if set. The bit is
cleared when LTSSM entered into Polling state.
High layer directs LTSSM to configuration state if set. The
bit is cleared when LTSSM entered into configuration
state.
High layer directs LTSSM to recovery state if set. The bit
is cleared when LTSSM entered into recovery state.
High layer directs LTSSM to external loopback master
state if set. The bit is cleared when LTSSM entered into
master external loopback state.
High layer directs LTSSM to hot reset state if set. The bit
is cleared when LTSSM exited out of the hot reset state.
High layer directs LTSSM to disable state if set. The bit is
cleared when LTSSM entered into disable state.
L N (O
INK UMBER FFSET

Table 464: PHY/Link Training Link Number (Offset 0x7E0C)

Description
–
Lane Number within component
L N (O
ANE UMBER FFSET

Table 465: PHY/Link Training Lane Number (Offset 0x7E10)

Description
–
Lane Number within link
Bro adco m Co rp or atio n
(O 0 7E08)
FFSET X
0 7E0C)
X
0 7E10)
X
BCM5722
Init Access
0 RO
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Init Access
0 RO
PAD RO
Init Access
0 RO
PAD RO
PCIe Registers Page 406