Table 441: Data Link Attention Register (Offset 0X7D08); Table 442: Data Link Attention Mask Register (Offset 0X7D0C) - Broadcom BCM5722 Programmer's Manual

Programmer's Guide
10/15/07
D L A
ATA INK TTENTION
Bit Field
31:5 Reserved
4 Data Link Layer Error
Attention Indicator
3 NAK Received Counter
Attention Indicator
2 DLLP Error Counter
Attention Indicator
1 TLP Bad Sequence
Counter Attention
Indicator
0 TLP Error Counter
Attention Indicator
D L A
ATA INK TTENTION
Bit Field
31:8 Reserved
7:5 Attention Mask
4 Data Link Layer Error
Attention Mask
3 NAK Received Counter
Attention Mask
2 DLLP Error Counter
Attention Mask
1 TLP Bad Sequence
Counter Attention Mask
0 TLP Error Counter
Attention Mask
Document 5722-PG101-R
R (O
EGISTER FFSET

Table 441: Data Link Attention Register (Offset 0x7D08)

Description
Write as 0, ignore when read.
Asserted when any of the following bits are set in the data
link status register:
• FC Update Timeout.
• FC Receive Overflow.
• FC Protocol Error.
• Data Link Protocol Error.
• Replay Rollover or Replay Timeout (read the
Link Status Register (Offset 0x7D04)" on page 397
clear this bit).
Set when NAK received counter value is greater than or
equal to attention threshold.
Cleared when counter is read.
Set when DLLP error counter value is greater than or
equal to attention threshold.
Cleared when counter is read.
Set when TLP bad sequence counter value is greater
than or equal to attention threshold.
Cleared when counter is read.
Set when TLP error counter value is greater than or equal
to attention threshold.
Cleared when counter is read.
M R
ASK EGISTER

Table 442: Data Link Attention Mask Register (Offset 0x7D0C)

Description
Write as 0, ignore when read.
Reserved for additional attention bits.
Data link error attention bit causes assertion of data link
attention output when mask bit is set to 1.
NAK received counter attention bit causes assertion of
data link attention output when mask bit is set to 1.
DLLP error counter attention bit causes assertion of data
link attention output when mask bit is set to 1.
TLP bad sequence counter attention bit causes assertion
of data link attention output when mask bit is set to 1.
TLP error counter attention bit causes assertion of data
link attention output when mask bit is set to 1.
Bro adco m Co rp or atio n
0 7D08)
X
(O 0 7D0C)
FFSET X
BCM5722
Init Access
0 –
0 RO
"Data
to
0 RO
0 RO
0 RO
0 RO
Init Access
0 RO
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
PCIe Registers Page 398