Figure 54: Read And Write Channels Of Dma Engine - Broadcom BCM5722 Programmer's Manual

BCM5722 Programmer's Guide
10/15/07
Register Read Using Indirect Mode
PCI_CFG_WRITE(Register_Base_Address, BCM57XXXRegAddr)
Value = PCI_CFG_READ(Register_Data_Register)
Register Write Using Indirect Mode
PCI_CFG_WRITE(Register_Base_Address, BCM57XXXRegAddr)
PCI_CFG_WRITE(Register_Data_Register, Value)
B I
US NTERFACE
D
ESCRIPTION
The read/write DMA engines both drive the PCIe interface. Normally, each DMA engine alternates bursts to the PCIe bus,
and both interfaces may have outstanding transactions on the PCI bus. The BCM5722 architecture identifies two
channels—a read DMA channel and a write DMA channel. Each channel corresponds to the appropriate DMA engine (see
Figure 54). The configuration of the DMA engines and the PCI interface is discussed in this section.
Read Channel Write Channel
DMA Write DMA Read
Engine Engine
Write FIFO Read FIFO
PCI Interface
PCIe Bus

Figure 54: Read and Write Channels of DMA Engine

Bro adco m C orp or atio n
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