Table 35: Recommended Bcm5722 Ethernet Controller Memory Pool Watermark Settings; Table 36: Recommended Bcm5722 Ethernet Controller Low Watermark Maximum Receive Frames' Settings - Broadcom BCM5722 Programmer's Manual

BCM5722
28. Configure MAC memory pool watermarks. Broadcom has run hardware simulations on the Mbuf usage and strongly
recommends the settings shown in
speeds. Host software must configure the MAC RX Mbuf Low Watermark and Mbuf High Watermark registers
MBUF Low Watermark Register (Offset 0x4414)" on page
on page 308) during initialization.

Table 35: Recommended BCM5722 Ethernet controller Memory Pool Watermark Settings

Register
MAC RX Mbuf Low Watermark
Mbuf High Watermark
Note: The Low WaterMark Max Receive Frames register (0x504) specifies the number of good frames to
receive after RxMbuf Low Watermark has been reached. The driver software should make sure that the MAC
RxMbuf Low WaterMark is greater than the number of Mbufs required for receiving the number of frames as
specified in 0x504. The first Mbuf in the Mbuf chain of a frame will have 80 bytes of packet data while each
of the subsequent Mbufs except the last Mbuf will have 120 bytes for packet data. The last Mbuf in the chain
will have the rest of the packet data which can be up to 120 bytes.
29. Configure flow control behavior when the Rx Mbuf low watermark level has been reached (see
Watermark Maximum Receive Frames Register (Offset 0x504)" on page
Table 36: Recommended BCM5722 Ethernet controller Low Watermark Maximum Receive Frames'
Register
Low Water Mark Maximum Receive Frames
30. Enable the buffer manager. The buffer manager handles the internal allocation of memory resources for send and
receive traffic. The Enable and Attn_Enable bits should be set in the Buffer Manager Mode register (see
Mode Register (Offset 0x4400)" on page
31. Poll for successful start of buffer manager. Poll the Enable bit in the Buffer Manager Mode register (see
Mode Register (Offset 0x4400)" on page
the previous step. The Enable bit will remain de-asserted until the buffer manager starts, at which point it will reflect an
asserted state.
32. Enable internal hardware queues. The MAC architecture uses internal queues to pass messages between functional
blocks. These messages coordinate RX/TX traffic flows. Device drivers need to enable these queues so the hardware
blocks can pass messages. Host software must set and then reset the bits in the FTQ Reset register (see
Register (Offset 0x5C00)" on page
a. First, host software should write 0xFFFFFFFF to the FTQ Reset register.
b. Second, host software should clear the FTQ Reset register by writing 0x00000000.
33. Initialize the Standard Receive Buffer Ring. Host software should write the Ring Control Block structure (see
Control Blocks" on page
Register (Offset 0x2450)" on page
based on allocation routines specific to the OS/RTOS.
settings.
Page 85 Initialization
Table 35. These settings/values will establish proper operation for 10/100/1000
306).
306) for 10 ms. This test ensures the buffer manager successfully starts from
326) to start internal queues:
44) to the Standard Receive BD Ring RCB register (see
287). Host software should be careful to initialize the host physical memory address
Bro adco m C orp or atio n
308, and "MBUF High Watermark Register (Offset 0x4418)"
Standard Ethernet Frames
0x20
0x60
258). See the note above in Step-28.
Settings
Bits Recommended Value
All 2
Table 37 shows the recommended Standard Ring Initialization
Programmer's Guide
("MAC RX
Table 36 and
"Buffer Manager
"Buffer Manager
"FTQ Reset
"Standard Receive BD Ring RCB
Document 5722-PG101-R
10/15/07
"Low
"Ring