Programmer's Guide
10/15/07
When wire speed mode is enabled, the HCD can be determined from MII register 19h, bits 10:8, since not all of MII register 4
advertised abilities may be sent to the Link Partner when downgrade is active, as shown by a 1 in bit 14 of MII register 11h.
PHY C
ONTROL
The BCM5722 Ethernet controller supports the following physical layer interfaces:
•
The MII is used in conjunction with 10-/100-Mbps copper Ethernet transceivers.
•
GMII supports 1000 Mbps copper Ethernet transceivers.
MII B
LOCK
The MII interconnects the MAC and PHY sublayers (see the following figure).
2.5 MHz at 10 Mbps
25 MHz at 100 Mbps
Physical Layer
Symbol
Decoder
LED
Control
Symbol
Encoder
2.5 MHz at 10 Mbps
25 MHz at 100 Mbps
Document
5722-PG101-R
MII
RXD /4
RX_CLK1
RX_ER
RX
RX_DV
I/O
COL
Media
CRS
Status
LNKRDY
LED
I/O
TXD /4
MII_TXCLK
TX
TX_ER
I/O
TX_EN
4-bit Data Path
Figure 18: Media Independent Interface
Bro adco m Co rp or atio n
4-bit Data Path
MAC Sublayer
RX Media
RX
Access
I/O
Mgmnt
I/O
TX
TX
Media
I/O
Access
Mgmnt
BCM5722
RX
Rx Data
Decapsulation
MAC
TX
Tx Data
Encapsulation
MAC
PHY Control
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