Figure 39: Header Region Registers - Broadcom BCM5722 Programmer's Manual

Programmer's Guide
10/15/07
The header region (see Figure
capabilities registers are optional; however, they must adhere to section 6.7 of the PCI SIIG 2.2 specification. Each capability
has a unique ID, which is well-defined. The capabilities are chained using the Next Caps field, in the capability register. The
last capability will have a Next Caps field, which is zeroed.
0x00
255
Bytes
0xFF
See the PCI configuration registers in
Document 5722-PG101-R
39) is required by the PCI 2.2 specification. These registers must be implemented. The
PCI
Configuration
Registers
Header Region
Capabilities

Figure 39: Header Region Registers

Section 12: "BCM5722 Ethernet Controller Register Definitions" on page
Bro adco m Co rp or atio n
0x00
0x04
0x08
0x0C
0x10
0x14
0x18
0x1C
0x20
Required
0x24
0x28
0x2C
0x30
0x34
0x38
0x3C
0x40
Capabilities
0x64
BCM5722
Bytes
03 02 01 00
Device ID Vendor ID
(0x14E4)
Status Command
Register Register
Class Code Rev ID
Cache
Hdr
Latency
BIST Line
Timer
Type
Size
BAR 1 (Lower 32 bits)
BAR 2 (Upper 32 bits)
BAR 3
Not Implemented
BAR 4
Not Implemented
BAR 5
Not Implemented
BAR 6
Not Implemented
Reserved
SubSystem SubSystem
ID Vendor ID
Expansion ROM
BAR
Caps
Reserved Ptr
(0x48)
Reserved
Max Min Int Int
Lat Gnt Pin Line
186.
Configuration Space Page 110