Motorola MPC533 Reference Manual page 57

Table
Number
13-13 CCW Bit Descriptions ............................................................................................ 13-30
13-14 Trigger Events ......................................................................................................... 13-55
13-15 Status Bits ............................................................................................................... 13-55
13-16 External Circuit Settling Time to 1/2 LSB (10-Bit Conversions).......................... 13-76
13-17 Error Resulting from Input Leakage (IOFF)........................................................... 13-77
14-1 QADC64E A Address Map....................................................................................... 14-4
14-2 Analog Input Channels.............................................................................................. 14-7
14-3 QADCMCR Bit Descriptions ................................................................................... 14-9
14-4 QADC64E Bus Error Response .............................................................................. 14-12
14-5 QADCINT Bit Descriptions.................................................................................... 14-13
14-6 PORTQA Bit Descriptions...................................................................................... 14-14
14-7 QACR0 Bit Descriptions ........................................................................................ 14-15
14-8 Prescaler f
SYSCLK
14-9 QACR1 Bit Descriptions ........................................................................................ 14-17
14-10 Queue 1 Operating Modes ...................................................................................... 14-18
14-11 QACR2 Bit Descriptions ........................................................................................ 14-19
14-12 Queue 2 Operating Modes ...................................................................................... 14-20
14-13 QASR0 Bit Descriptions ......................................................................................... 14-22
14-14 Pause Response ....................................................................................................... 14-26
14-15 Queue Status ........................................................................................................... 14-26
14-16 QASR1 Bit Descriptions ......................................................................................... 14-28
14-17 CCW Bit Descriptions ............................................................................................ 14-32
14-18 QADC64E_A Multiplexed Channel Assignments and Signal Designations.......... 14-33
14-19 QADC64E Clock Programmability ........................................................................ 14-52
14-20 Trigger Events ......................................................................................................... 14-56
14-21 Status Bits ............................................................................................................... 14-56
14-22 External Circuit Settling Time to 1/2 LSB (10-Bit Conversions)........................... 14-77
14-23 Error Resulting From Input Leakage (IOFF).......................................................... 14-78
15-1 QSMCM Register Map ............................................................................................. 15-4
15-2 QSMCM Global Registers ........................................................................................ 15-6
15-3 Interrupt Levels ......................................................................................................... 15-8
15-4 QSMCMMCR Bit Descriptions................................................................................ 15-9
15-5 QDSCI_IL Bit Descriptions.................................................................................... 15-10
15-6 QSPI_IL Bit Descriptions ....................................................................................... 15-10
15-7 QSMCM Pin Control Registers .............................................................................. 15-11
15-8 Effect of DDRQS on QSPI Pin Function................................................................ 15-11
15-9 QSMCM Pin Functions........................................................................................... 15-13
15-10 PQSPAR Bit Descriptions....................................................................................... 15-13
15-11 DDRQS Bit Descriptions ........................................................................................ 15-14
15-12 QSPI Register Map ................................................................................................. 15-17
15-13 SPCR0 Bit Descriptions......................................................................................... 15-19
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Tables
Title
Divide-by Values....................................................................... 14-16
Tables
Page
Number
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