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Table
Number
6-14
SIU Interrupt Controller – Bit Acronym Definitions................................................ 6-33
6-15
SYPCR Bit Descriptions .......................................................................................... 6-39
6-16
SWSR Bit Descriptions............................................................................................ 6-40
6-17
TESR Bit Descriptions............................................................................................. 6-41
6-18
TBSCR Bit Descriptions .......................................................................................... 6-43
6-19
RTCSC Bit Descriptions .......................................................................................... 6-44
6-20
PISCR Bit Descriptions ........................................................................................... 6-46
6-21
PITC Bit Descriptions .............................................................................................. 6-47
6-22
PIT Bit Descriptions................................................................................................. 6-47
6-23
SGPIODT1 Bit Descriptions.................................................................................... 6-48
6-24
SGPIODT2 Bit Descriptions.................................................................................... 6-48
6-25
SGPIOCR Bit Descriptions...................................................................................... 6-49
6-26
Data Direction Control.............................................................................................. 6-49
7-1
Reset Action Taken For Each Reset Cause ................................................................. 7-4
7-2
Reset Configuration Word and Data Corruption/Coherency ...................................... 7-5
7-3
Reset Status Register Bit Descriptions........................................................................ 7-6
7-4
Reset Configuration Options....................................................................................... 7-7
7-5
RCW Bit Descriptions .............................................................................................. 7-12
8-1
Reset Clocks Source Configuration .......................................................................... 8-10
8-2
TMBCLK Divisions.................................................................................................. 8-10
8-3
Status of Clock Source .............................................................................................. 8-16
8-4
Power Mode Control Bit Settings ............................................................................ 8-17
8-5
Power Mode Descriptions ........................................................................................ 8-17
8-6
Power Mode Wake-Up Operation ............................................................................ 8-19
8-7
Power Supplies......................................................................................................... 8-22
8-8
KAPWR Registers and Key Registers ...................................................................... 8-25
8-9
SCCR Bit Descriptions ............................................................................................. 8-30
8-10
COM and CQDS Bits Functionality ......................................................................... 8-33
8-11
PLPRCR Bit Descriptions........................................................................................ 8-34
8-12
COLIR Bit Descriptions........................................................................................... 8-36
8-13
VSRMCR Bit Descriptions ...................................................................................... 8-37
9-1
MPC533 SIU Signals .................................................................................................. 9-4
9-2
Data Bus Requirements For Read Cycles ................................................................. 9-31
9-3
Data Bus Contents for Write Cycles ......................................................................... 9-32
9-4
Priority Between Internal and External Masters over External Bus ......................... 9-36
9-5
4 Word Burst Length and Order................................................................................ 9-39
9-6
BURST/TSIZE Encoding ......................................................................................... 9-39
9-7
Address Type Pins..................................................................................................... 9-40
9-8
Address Types Definition.......................................................................................... 9-41
9-9
Termination Signals Protocol.................................................................................... 9-51
10-1
Timing Requirements for Reduced Setup Time........................................................ 10-7
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
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